[Intel-gfx] [PATCH 2/2] drm/i915: Remove fence pipelining infrastructure
daniel at ffwll.ch
Fri Mar 23 20:18:37 CET 2012
On Thu, Mar 22, 2012 at 03:10:01PM +0000, Chris Wilson wrote:
> I have failed to find a way to make this work without random GPU deaths,
> so remove the ability to pipeline a fence update using the GPU. In the
> process, we can refactor the code to improve the error handling and
> avoid unnecessary modifications to our VMA if we do not need to update
> the fence register.
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Mea culpa, but I agree that it's better to reap this instead of letting it
languish even longer as some dead code. For the patch itself, this does
way too much. Imo the gem_write_fence rework and the reaping of the
pipelining logic should be separate patches (maybe even more) - I don't
quite see through this patch and follow where things move to.
Maybe also add some more comments about the lifetime rules wrt obj->ring
obj->last_rendering_seqno and obj->last_fenced_seqno.
Also, if you have any ideas for crazy i-g-t tests, I think we should use
this opportunity to fill some of the gapping wholes wrt fencing we have in
And to pardon dense me: What does VMA mean in this context?
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
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