[Intel-gfx] [PATCH 2/2] drm/i915: Remove fence pipelining infrastructure

Chris Wilson chris at chris-wilson.co.uk
Fri Mar 23 21:02:05 CET 2012

On Fri, 23 Mar 2012 20:18:37 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Thu, Mar 22, 2012 at 03:10:01PM +0000, Chris Wilson wrote:
> > I have failed to find a way to make this work without random GPU deaths,
> > so remove the ability to pipeline a fence update using the GPU. In the
> > process, we can refactor the code to improve the error handling and
> > avoid unnecessary modifications to our VMA if we do not need to update
> > the fence register.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Mea culpa, but I agree that it's better to reap this instead of letting it
> languish even longer as some dead code. For the patch itself, this does
> way too much. Imo the gem_write_fence rework and the reaping of the
> pipelining logic should be separate patches (maybe even more) - I don't
> quite see through this patch and follow where things move to.

I got bored of rewriting the same 200 lines with the incremental churn.
Every patch only made sense as "preparing to rip out pipelining".

> Maybe also add some more comments about the lifetime rules wrt obj->ring
> obj->last_rendering_seqno and obj->last_fenced_seqno.
> Also, if you have any ideas for crazy i-g-t tests, I think we should use
> this opportunity to fill some of the gapping wholes wrt fencing we have in
> our testuite.

The obvious failure conditions all seem to revolve around racing with
pending GPU writes, those should be hit by gem_stress. The less
obvious ones where the GPU dies and everything in the error state looks
consistent and coherent, I haven't a clue. I was up to a couple of hours
between failure and still do not why it failed. With pipelining
disabled, that failure mode vanishes. 

> And to pardon dense me: What does VMA mean in this context?

Exactly what you think, virtual memory area. It is a hint that with
certain access patterns, you can see a significant performance
improvement with this patch, can you spot why? ;-) (Though I don't think
mesa would see any benefit.)

Chris Wilson, Intel Open Source Technology Centre

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