[Intel-gfx] [PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers
Rodrigo Vivi
rodrigo.vivi at gmail.com
Mon Mar 26 19:36:15 CEST 2012
* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov at intel.com> wrote:
> There is one instance of those registers for each DDI port.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3831fe7..2927460 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3914,4 +3914,27 @@
> #define DP_TP_STATUS_E 0x64444
> #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
>
> +/* DDI Buffer Control */
> +#define DDI_BUF_CTL_A 0x64000
> +#define DDI_BUF_CTL_B 0x64100
> +#define DDI_BUF_CTL_C 0x64200
> +#define DDI_BUF_CTL_D 0x64300
> +#define DDI_BUF_CTL_E 0x64400
> +#define DDI_BUF_CTL_ENABLE (1<<31)
> +#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
> +#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
> +#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
> +#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
> +#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
> +#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
> +#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
> +#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
> +#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
> +#define DDI_BUF_EMP_MASK (0xf<<24)
> +#define DDI_BUF_IS_IDLE (1<<7)
> +#define DDI_PORT_WIDTH_X1 (0<<1)
> +#define DDI_PORT_WIDTH_X2 (1<<1)
> +#define DDI_PORT_WIDTH_X4 (3<<1)
> +#define DDI_INIT_DISPLAY_DETECTED (1<<0)
> +
> #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net
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