[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)
Patchwork
patchwork at emeril.freedesktop.org
Fri Apr 7 01:13:02 UTC 2017
== Series Details ==
Series: series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3)
URL : https://patchwork.freedesktop.org/series/22607/
State : warning
== Summary ==
Series 22607v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/22607/revisions/3/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-bxt-t5700)
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time: 438s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time: 426s
fi-bsw-n3050 total:278 pass:242 dwarn:0 dfail:0 fail:0 skip:36 time: 565s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time: 511s
fi-bxt-t5700 total:278 pass:257 dwarn:1 dfail:0 fail:0 skip:20 time: 548s
fi-byt-j1900 total:278 pass:254 dwarn:0 dfail:0 fail:0 skip:24 time: 490s
fi-byt-n2820 total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 478s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 408s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time: 407s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time: 430s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 493s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 467s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time: 454s
fi-kbl-7560u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 567s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 450s
fi-skl-6700hq total:278 pass:261 dwarn:0 dfail:0 fail:0 skip:17 time: 580s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time: 461s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time: 487s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time: 429s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time: 530s
fi-snb-2600 total:278 pass:249 dwarn:0 dfail:0 fail:0 skip:29 time: 402s
7aafd5c8395fea9a79fbee82de4ffc63c04790d6 drm-tip: 2017y-04m-06d-21h-02m-00s UTC integration manifest
7624f54 drm/i915/cnl: Adjust min pixel rate.
3378c91 drm/i915/cnl: LSPCON support is gen9+
8b06dc4 drm/i915/cnl: Enable Audio Pin Buffer.
d2c1f3f drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod)
08465fd drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
b4d1879 drm/i915/cnl: Add support slice/subslice/eu configs
2b1a220 drm/i915/cnl: Setup PAT Index.
7b4497d drm/i915/cnl: Enable fifo underrun for Cannonlake.
7833f55 drm/i915/cnl: Fix Cannonlake scaler mode programing.
96f694b drm/i915/cnl: Cannonlake color init.
dfe9719 x86/gpu: CNL uses the same GMS values as SKL
bdb4899 drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
bbee9e7 drm/i915/gen10: implement gen 10 watermarks calculations
7b85e06 drm/i915/gen10: fix WM latency printing
62d4e30 drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+
c0a1786 drm/i915/gen10: fix the gen 10 SAGV block time
55462a3 drm/i915/cnl: Enable SAGV for Cannonlake.
f73c379 drm/i915/gen10+: use the SKL code for reading WM latencies
9b050c9 drm/i915/cnl: Avoid old DDI translation functions on Cannonlake.
39c17e6 drm/i915/cnl: Get DDI clock based on PLLs.
e40493b drm/i915/cnl: Dump the right pll registers when dumping pipe config.
39258f0 drm/i915/cnl: Add allowed DP rates for Cannonlake.
04e9b41 drm/i915/cnl: Add max allowed Cannonlake DC.
f1d4b71 drm/i915/cnl: DC3 to DC5 counters available on CNL.
232cc4b drm/i915: Use HAS_CSR instead of gen number on DMC load.
9ecef92 drm/i915/DMC/CNL: Load DMC on CNL
9073eae drm/i915/cnl: Add slice and subslice information to debugfs.
fb45b88 drm/i915/cnl: Enable loadgen_select bit for vswing sequence
e2d0803 drm/i915/cnl: Implement voltage swing sequence.
d4edcf00 drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.
aadad4a drm/i915/cnl: Add registers related to voltage swing sequences.
af4d0d1 drm/i915: Add MMIO helper for 6 ports with different offsets.
0b62b8f drm/i915/cnl: Enable wrpll computation for CNL
52b5618 drm/i915/cnl: Initialize PLLs
383b9b6 drm/i915: Configure DPLL's for Cannonlake
49011b6 drm/i915/cnl: DDI - PLL mapping
e6a5ead drm/i915/cnl: Allow dynamic cdclk changes on CNL
07e5df5 drm/i915/cnl: Implement CNL display init/unit sequence
55eada5 drm/i915/cnl: Implement .set_cdclk() for CNL
6ac53af drm/i915/cnl: Implement .get_display_clock_speed() for CNL
4923ac5 drm/i915/cnl: Also need power well sanitize.
4298771 drm/i915/cnl: Add power wells for CNL
39a5338 drm/i915/cnl: Inherit RPS stuff from previous platforms.
96ec06c drm/i915/cnl: Add force wake for gen10.
608930b drm/i915/gen10: Set value of Indirect Context Offset for gen10
ff47c55 drm/i915/cnl: Add RT cache flush pipe control w/a
263a836 drm/i915/cnl: Update the context size
098c373 drm/i915/cnl: Cannonlake has same MOCS table than Skylake.
c823a26 drm/i915/cnl: Configure EU slice power gating.
9b6fbd8 drm/i915/cnl: Add initial gen10 golden states.
1f3d6ae drm/i915/cnl: CNL has an increased DDB size
0dbc7aa drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe
89443b5 drm/i915/cnl: Apply large line width optimization
6dc1125 drm/i915/cnl: WaDisableEnhancedSBEVertexCaching
3cfc58c drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization
5218894 drm/i915/cnl: Introduce initial Cannonlake Workarounds.
48a37d5 drm/i915/cnl: add IS_CNL_REVID macro
8ec25d8 drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
e4323e4 drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
8410481 drm/i915/cnl: Cannonlake uses CNP PCH.
b9a3231 drm/i915/cnl: Introduce Cannonlake platform defition.
21bf60c drm/i915/cnp: Panel Power sequence changes for CNP PCH.
3270f68 drm/i915/cnp: add CNP gmbus support
d2a3b99 drm/i915/cnp: Add Backlight support to CNP PCH.
3f611350b drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
1d21ab6 drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH
631938c drm/i915/cnp: Introduce Cannonpoint PCH.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4434/
More information about the Intel-gfx
mailing list