[Intel-gfx] [PATCH 1/3] drm/i915: Enable render context support for Ironlake (gen5)

[Ville Syrjälä]

On Thu, Nov 23, 2017 at 07:46:23PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 23, 2017 at 04:27:48PM +0000, Chris Wilson wrote:
> > Ironlake does support being able to saving and reloading context specific
> > registers between contexts, providing isolation of the basic GPU state
> > (as programmable by userspace). This allows userspace to assume that the
> > GPU retains their state from one batch to the next, minimising the
> > amount of state it needs to reload.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c  | 2 ++
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
> >  2 files changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index fede62daf3e1..88ef00faf576 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -175,6 +175,8 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
> >  			return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
> >  					PAGE_SIZE);
> >  		case 5:
> > +			cxt_size = I915_READ(CXT_SIZE);
> > +			return round_up(cxt_size * 64, PAGE_SIZE);
> 
> I don't think this is correct. It misses the non-pipelined 3D state,
> and the ring stuff at the start which IIRC at least SNB still
> saved even though it's not used in ring buffer mode. So I think
> this needs a 0xb added to the CXT_SIZE value.
> 
> But even that doesn't really match the docs. The context image layout
> is shown to be 0x3b cachelines long, but 0xb+0x2d only gets us to
> 0x38. So it looks like CXT_SIZE is off by two for some reason.

Oh. Actually CXT_SIZE is documented to be U5-1 on pre-SNB, so I
guess it's only off by one at most.

-- 
Ville Syrjälä
Intel OTC