[Intel-gfx] [PATCH] drm/i915/hsw: add missing disabled EUs registers reads

[Joonas Lahtinen]

Quoting Lionel Landwerlin (2018-02-16 17:31:01)
> +static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +       struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +       struct sseu_dev_info *sseu = &info->sseu;
> +       u32 fuse1;
> +
> +       /*
> +        * There isn't a register to tell us how many slices/subslices. We
> +        * work off the PCI-ids here.
> +        */
> +       switch (info->gt) {
> +       case 1:
> +               sseu->slice_mask = BIT(0);
> +               sseu->subslice_mask = BIT(0);
> +               break;
> +       case 2:
> +               sseu->slice_mask = BIT(0);
> +               sseu->subslice_mask = BIT(0) | BIT(1);
> +               break;
> +       case 3:
> +               sseu->slice_mask = BIT(0) | BIT(1);
> +               sseu->subslice_mask = BIT(0) | BIT(1);
> +               break;
> +       default:
> +               GEM_BUG_ON(true);

MISSING_CASE() and maybe return GT1 values in the default case? So how
about:

	default:
		MISSING_CASE(info->gt);
	case 1:
		...

> +               break;
> +       }
> +
> +       fuse1 = I915_READ(HSW_PAVP_FUSE1);
> +       switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> +       case HSW_F1_EU_DIS_MASK_10EUS:
> +               sseu->eu_per_subslice = 10;
> +               break;
> +       case HSW_F1_EU_DIS_MASK_8EUS:
> +               sseu->eu_per_subslice = 8;
> +               break;
> +       case HSW_F1_EU_DIS_MASK_6EUS:
> +               sseu->eu_per_subslice = 6;
> +               break;
> +       default:
> +               GEM_BUG_ON(true);
> +               break;

Ditto.

With at least s/GEM_BUG_ON(true)/MISSING_CASE(val)/, this is:

Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>

Regards, Joonas