[Intel-gfx] [PATCH v2] drm/i915: Trim gen11_gt_irq_handler

[Chris Wilson]

Quoting Chris Wilson (2018-03-09 01:33:08)
>  gen11_gt_engine_intr(struct drm_i915_private * const i915,
>                      const unsigned int bank, const unsigned int bit)
> @@ -2836,10 +2798,23 @@ static void
>  gen11_gt_irq_handler(struct drm_i915_private * const i915,
>                      const u32 master_ctl)
>  {
> +       static const u8 bank0_map[] = {
> +               [GEN11_RCS0] = RCS,
> +               [GEN11_BCS]  = BCS,

Is there a reason why its RCS0 but BCS? And the multi-instance classes
actually use VCS(x)?
-Chris