[Intel-gfx] [PATCH v2] drm/i915: Trim gen11_gt_irq_handler

Tvrtko Ursulin tvrtko.ursulin at linux.intel.com
Fri Mar 9 10:06:48 UTC 2018

On 09/03/2018 01:38, Chris Wilson wrote:
> Quoting Chris Wilson (2018-03-09 01:33:08)
>>   gen11_gt_engine_intr(struct drm_i915_private * const i915,
>>                       const unsigned int bank, const unsigned int bit)
>> @@ -2836,10 +2798,23 @@ static void
>>   gen11_gt_irq_handler(struct drm_i915_private * const i915,
>>                       const u32 master_ctl)
>>   {
>> +       static const u8 bank0_map[] = {
>> +               [GEN11_RCS0] = RCS,
>> +               [GEN11_BCS]  = BCS,

> Is there a reason why its RCS0 but BCS? And the multi-instance classes
> actually use VCS(x)?

I am pretty sure that naming came from the spec.

Side note - one thing I dislike a bit about the current code and this 
patch is that all engines have to be enumerated explicitly in the 
interrupt handler. I kind of thought it was handy to handle the 
multi-class engines from a loop, and so have one place less to remember 
to update after adding a new engine instance.

And in general I think too many bike-sheds on this area of code before 
we are even running it on real hw. :(



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