[Intel-gfx] [PATCH CI 0/7] ICL reviewed mergeable patches

[Paulo Zanoni]

Let's see that the CI has to say about them before we merge them.

These are taken from: [PATCH 00/17] ICL PLLs, DP/HDMI and misc display

Dhinakaran Pandiyan (1):
  drm/i915/icl: HPD pin for port F

James Ausmus (1):
  drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL

Manasi Navare (4):
  drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
  drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
  drm/i915/icl: Add register defs for voltage swing sequences for MG PHY
    DDI
  drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer

Nabendu Maiti (1):
  drm/i915/icl: Added 5k source scaling support for Gen11 platform

 drivers/gpu/drm/i915/i915_drv.h      |   1 +
 drivers/gpu/drm/i915/i915_reg.h      | 164 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c     | 119 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  19 ++--
 drivers/gpu/drm/i915/intel_drv.h     |   4 +
 drivers/gpu/drm/i915/intel_hotplug.c |   3 +
 6 files changed, 302 insertions(+), 8 deletions(-)

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2.14.3