[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit

[Patchwork]

== Series Details ==

Series: series starting with [v3,01/10] drm: Add DP PSR2 sink enable bit
URL   : https://patchwork.freedesktop.org/series/40839/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
83dbb7136992 drm: Add DP PSR2 sink enable bit
36672bef768d drm: Add DP last received PSR SDP VSC register and bits
94b7edc3476d drm/i915/psr: Nuke aux frame sync
bbb38da76ef1 drm/i915/psr: Tie PSR2 support to Y coordinate requirement
1aed83cc161c drm/i915/psr/cnl: Enable Y-coordinate support in source
-:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:4061:
+#define   EDP_Y_COORDINATE_VALID	(1<<26) /* GLK and CNL+ */
                                 	  ^

-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:4062:
+#define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
                                  	  ^

-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:7069:
+#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1<<25) /* GLK and CNL+ */
                                       	  ^

total: 0 errors, 0 warnings, 3 checks, 43 lines checked
d4917260c5dc drm/i915/psr: Do not override PSR2 sink support
5a0735899e2a drm/i915/psr: Use PSR2 macro for PSR2
1c7cd16261ad drm/i915/psr: Cache sink synchronization latency
9cccb64694f4 drm/i915/psr: Set DPCD PSR2 enable bit when needed
b67c98399777 drm/i915/debugfs: Print sink PSR status