[Intel-gfx] [PATCH 6/8] drm/i915: Add calc_voltage_level display vfunc
Ville Syrjälä
ville.syrjala at linux.intel.com
Tue Sep 10 12:41:21 UTC 2019
On Fri, Sep 06, 2019 at 05:21:41PM -0700, Matt Roper wrote:
> With all of the cdclk function consolidation, we can cut down on a lot
> of platform if/else logic by creating a vfunc that's initialized at
> startup.
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 76 ++++++++--------------
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 2 files changed, 28 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a70fec82d2bc..a6696697a09f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1403,18 +1403,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> * Can't read this out :( Let's assume it's
> * at least what the CDCLK frequency requires.
> */
> - if (IS_ELKHARTLAKE(dev_priv))
> - cdclk_state->voltage_level =
> - ehl_calc_voltage_level(cdclk_state->cdclk);
> - else if (INTEL_GEN(dev_priv) >= 11)
> - cdclk_state->voltage_level =
> - icl_calc_voltage_level(cdclk_state->cdclk);
> - else if (INTEL_GEN(dev_priv) >= 10)
> - cdclk_state->voltage_level =
> - cnl_calc_voltage_level(cdclk_state->cdclk);
> - else
> - cdclk_state->voltage_level =
> - bxt_calc_voltage_level(cdclk_state->cdclk);
> + cdclk_state->voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk_state->cdclk);
> }
>
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1681,7 +1671,8 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> */
> cdclk_state.cdclk = calc_cdclk(dev_priv, 0);
> cdclk_state.vco = calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> - cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_state.voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
> @@ -1692,18 +1683,8 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.bypass;
> cdclk_state.vco = 0;
> - if (IS_ELKHARTLAKE(dev_priv))
> - cdclk_state.voltage_level =
> - ehl_calc_voltage_level(cdclk_state.cdclk);
> - else if (INTEL_GEN(dev_priv) >= 11)
> - cdclk_state.voltage_level =
> - icl_calc_voltage_level(cdclk_state.cdclk);
> - else if (INTEL_GEN(dev_priv) >= 10)
> - cdclk_state.voltage_level =
> - cnl_calc_voltage_level(cdclk_state.cdclk);
> - else
> - cdclk_state.voltage_level =
> - bxt_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_state.voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
> @@ -1739,12 +1720,8 @@ static void icl_init_cdclk(struct drm_i915_private *dev_priv)
> sanitized_state.cdclk = calc_cdclk(dev_priv, 0);
> sanitized_state.vco = calc_cdclk_pll_vco(dev_priv,
> sanitized_state.cdclk);
> - if (IS_ELKHARTLAKE(dev_priv))
> - sanitized_state.voltage_level =
> - ehl_calc_voltage_level(sanitized_state.cdclk);
> - else
> - sanitized_state.voltage_level =
> - icl_calc_voltage_level(sanitized_state.cdclk);
> + sanitized_state.voltage_level =
> + dev_priv->display.calc_voltage_level(sanitized_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
> }
> @@ -1763,7 +1740,8 @@ static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = calc_cdclk(dev_priv, 0);
> cdclk_state.vco = calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
> - cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
> + cdclk_state.voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
> @@ -2255,7 +2233,7 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> state->cdclk.logical.voltage_level =
> - bxt_calc_voltage_level(cdclk);
> + dev_priv->display.calc_voltage_level(cdclk);
>
> if (!state->active_pipes) {
> cdclk = calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> @@ -2264,7 +2242,7 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
> state->cdclk.actual.vco = vco;
> state->cdclk.actual.cdclk = cdclk;
> state->cdclk.actual.voltage_level =
> - bxt_calc_voltage_level(cdclk);
> + dev_priv->display.calc_voltage_level(cdclk);
> } else {
> state->cdclk.actual = state->cdclk.logical;
> }
> @@ -2319,14 +2297,9 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> state->cdclk.logical.vco = vco;
> state->cdclk.logical.cdclk = cdclk;
> - if (IS_ELKHARTLAKE(dev_priv))
> - state->cdclk.logical.voltage_level =
> - max(ehl_calc_voltage_level(cdclk),
> - cnl_compute_min_voltage_level(state));
> - else
> - state->cdclk.logical.voltage_level =
> - max(icl_calc_voltage_level(cdclk),
> - cnl_compute_min_voltage_level(state));
> + state->cdclk.logical.voltage_level =
> + max(dev_priv->display.calc_voltage_level(cdclk),
> + cnl_compute_min_voltage_level(state));
>
> if (!state->active_pipes) {
> cdclk = calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
> @@ -2334,12 +2307,8 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
>
> state->cdclk.actual.vco = vco;
> state->cdclk.actual.cdclk = cdclk;
> - if (IS_ELKHARTLAKE(dev_priv))
> - state->cdclk.actual.voltage_level =
> - ehl_calc_voltage_level(cdclk);
> - else
> - state->cdclk.actual.voltage_level =
> - icl_calc_voltage_level(cdclk);
> + state->cdclk.actual.voltage_level =
> + dev_priv->display.calc_voltage_level(cdclk);
> } else {
> state->cdclk.actual = state->cdclk.logical;
> }
> @@ -2563,19 +2532,28 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv)
> */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + dev_priv->display.set_cdclk = bxt_set_cdclk;
> + dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> + dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> + dev_priv->cdclk.table = icl_cdclk_table;
> + dev_priv->cdclk.table_size = ARRAY_SIZE(icl_cdclk_table);
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
> + dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> dev_priv->cdclk.table = icl_cdclk_table;
> dev_priv->cdclk.table_size = ARRAY_SIZE(icl_cdclk_table);
> } else if (IS_CANNONLAKE(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
> + dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;
> dev_priv->cdclk.table = cnl_cdclk_table;
> dev_priv->cdclk.table_size = ARRAY_SIZE(cnl_cdclk_table);
> } else if (IS_GEN9_LP(dev_priv)) {
> dev_priv->display.set_cdclk = bxt_set_cdclk;
> dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> + dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
> dev_priv->cdclk.table = bxt_cdclk_table;
> dev_priv->cdclk.table_size = ARRAY_SIZE(bxt_cdclk_table);
> } else if (IS_GEN9_BC(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a4d249193dc8..a56da431bfe3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -276,6 +276,7 @@ struct drm_i915_display_funcs {
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> void (*update_wm)(struct intel_crtc *crtc);
> int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> + u8 (*calc_voltage_level)(int cdclk);
> /* Returns the active state of the crtc, and if the crtc is active,
> * fills out the pipe-config with the hw state. */
> bool (*get_pipe_config)(struct intel_crtc *,
> --
> 2.20.1
--
Ville Syrjälä
Intel
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