[Intel-gfx] [PATCH] drm/i915: Allow set context SSEU on platforms after gen 11

[Summers, Stuart]

On Wed, 2019-09-18 at 13:39 -0700, Daniele Ceraolo Spurio wrote:
> 
> On 9/18/19 10:31 AM, Stuart Summers wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110559
> > 
> 
> What's the planned usage here? TGL HW only supports slice-level 
> power-gating and with only 1 slice on TGL we don't really have a
> choice 
> of what to program, do we?

Well, we do claim powergate support on TGL, so I assumed we'd want to
enable this path. Maybe I'm missing something though. Had a similar
response to Tvrtko.

Thanks,
Stuart

> 
> Daniele
> 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
> > Signed-off-by: Stuart Summers <stuart.summers at intel.com>
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > index f1c0e5d958f3..39af4c81b29a 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> > @@ -1310,7 +1310,7 @@ static int set_sseu(struct i915_gem_context
> > *ctx,
> >   	if (args->size < sizeof(user_sseu))
> >   		return -EINVAL;
> >   
> > -	if (!IS_GEN(i915, 11))
> > +	if (INTEL_GEN(i915) < 11)
> >   		return -ENODEV;
> >   
> >   	if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
> > 
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