[intel-gvt-linux:topic/gvt-xengt 22/31] drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
kbuild test robot
fengguang.wu at intel.com
Mon Dec 25 12:39:03 UTC 2017
tree: https://github.com/intel/gvt-linux topic/gvt-xengt
head: 9cac0922ebda9b50c7c2736edd7b942d75bd4fea
commit: 0c56d7a44e7019c393f54bcc07b1ddb1cc53e4c1 [22/31] drm/i915/gvt: Retrieve the guest gm base address from PVINFO
config: x86_64-randconfig-s1-12251841 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout 0c56d7a44e7019c393f54bcc07b1ddb1cc53e4c1
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/gvt/gtt.c:38:0:
drivers/gpu/drm/i915/gvt/gtt.c: In function 'intel_gvt_ggtt_validate_range':
>> drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
>> drivers/gpu/drm/i915/gvt/gvt.h:398:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:402:47: note: in expansion of macro 'vgpu_guest_aperture_offset'
#define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:484:13: note: in expansion of macro 'vgpu_guest_aperture_gmadr_base'
((gmadr >= vgpu_guest_aperture_gmadr_base(vgpu)) && \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:492:5: note: in expansion of macro 'vgpu_gmadr_is_aperture'
((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gtt.c:51:8: note: in expansion of macro 'vgpu_gmadr_is_valid'
if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
>> drivers/gpu/drm/i915/gvt/gvt.h:398:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:402:47: note: in expansion of macro 'vgpu_guest_aperture_offset'
#define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:404:3: note: in expansion of macro 'vgpu_guest_aperture_gmadr_base'
(vgpu_guest_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:485:13: note: in expansion of macro 'vgpu_guest_aperture_gmadr_end'
(gmadr <= vgpu_guest_aperture_gmadr_end(vgpu)))
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:492:5: note: in expansion of macro 'vgpu_gmadr_is_aperture'
((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gtt.c:51:8: note: in expansion of macro 'vgpu_gmadr_is_valid'
if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:400:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:406:45: note: in expansion of macro 'vgpu_guest_hidden_offset'
#define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:488:13: note: in expansion of macro 'vgpu_guest_hidden_gmadr_base'
((gmadr >= vgpu_guest_hidden_gmadr_base(vgpu)) && \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:493:5: note: in expansion of macro 'vgpu_gmadr_is_hidden'
(vgpu_gmadr_is_hidden(vgpu, gmadr))))
^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gtt.c:51:8: note: in expansion of macro 'vgpu_gmadr_is_valid'
if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:400:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:406:45: note: in expansion of macro 'vgpu_guest_hidden_offset'
#define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:408:3: note: in expansion of macro 'vgpu_guest_hidden_gmadr_base'
(vgpu_guest_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/gvt.h:489:13: note: in expansion of macro 'vgpu_guest_hidden_gmadr_end'
(gmadr <= vgpu_guest_hidden_gmadr_end(vgpu)))
^~~~~~~~~~~~~~~~~~~~~~~~~~~
--
In file included from drivers/gpu/drm/i915/gvt/cfg_space.c:35:0:
drivers/gpu/drm/i915/gvt/cfg_space.c: In function 'map_aperture':
>> drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
>> drivers/gpu/drm/i915/gvt/gvt.h:398:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/cfg_space.c:139:21: note: in expansion of macro 'vgpu_guest_aperture_offset'
first_gfn = (val + vgpu_guest_aperture_offset(vgpu)) >> PAGE_SHIFT;
^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +434 drivers/gpu/drm/i915/gvt/gvt.h
28a60dee2 Zhi Wang 2016-09-02 395
0c56d7a44 Yulei Zhang 2017-05-27 396 /* Aperture/GM space definitions for vGPU Guest view point */
0c56d7a44 Yulei Zhang 2017-05-27 397 #define vgpu_guest_aperture_offset(vgpu) \
0c56d7a44 Yulei Zhang 2017-05-27 @398 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
0c56d7a44 Yulei Zhang 2017-05-27 399 #define vgpu_guest_hidden_offset(vgpu) \
0c56d7a44 Yulei Zhang 2017-05-27 @400 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
0c56d7a44 Yulei Zhang 2017-05-27 401
0c56d7a44 Yulei Zhang 2017-05-27 @402 #define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(vgpu))
0c56d7a44 Yulei Zhang 2017-05-27 403 #define vgpu_guest_aperture_gmadr_end(vgpu) \
0c56d7a44 Yulei Zhang 2017-05-27 404 (vgpu_guest_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
0c56d7a44 Yulei Zhang 2017-05-27 405
0c56d7a44 Yulei Zhang 2017-05-27 @406 #define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu))
0c56d7a44 Yulei Zhang 2017-05-27 407 #define vgpu_guest_hidden_gmadr_end(vgpu) \
0c56d7a44 Yulei Zhang 2017-05-27 408 (vgpu_guest_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
0c56d7a44 Yulei Zhang 2017-05-27 409
28a60dee2 Zhi Wang 2016-09-02 410 struct intel_vgpu_creation_params {
28a60dee2 Zhi Wang 2016-09-02 411 __u64 handle;
28a60dee2 Zhi Wang 2016-09-02 412 __u64 low_gm_sz; /* in MB */
28a60dee2 Zhi Wang 2016-09-02 413 __u64 high_gm_sz; /* in MB */
28a60dee2 Zhi Wang 2016-09-02 414 __u64 fence_sz;
d1a513be1 Zhenyu Wang 2017-02-24 415 __u64 resolution;
28a60dee2 Zhi Wang 2016-09-02 416 __s32 primary;
28a60dee2 Zhi Wang 2016-09-02 417 __u64 vgpu_id;
bc90d097a Ping Gao 2017-03-30 418
bc90d097a Ping Gao 2017-03-30 419 __u32 weight;
28a60dee2 Zhi Wang 2016-09-02 420 };
28a60dee2 Zhi Wang 2016-09-02 421
28a60dee2 Zhi Wang 2016-09-02 422 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
28a60dee2 Zhi Wang 2016-09-02 423 struct intel_vgpu_creation_params *param);
d22a48bf7 Changbin Du 2017-01-13 424 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
28a60dee2 Zhi Wang 2016-09-02 425 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
28a60dee2 Zhi Wang 2016-09-02 426 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
28a60dee2 Zhi Wang 2016-09-02 427 u32 fence, u64 value);
28a60dee2 Zhi Wang 2016-09-02 428
90551a129 Zhenyu Wang 2017-12-19 429 /* Macros for easily accessing vGPU virtual/shadow register.
90551a129 Zhenyu Wang 2017-12-19 430 Explicitly seperate use for typed MMIO reg or real offset.*/
90551a129 Zhenyu Wang 2017-12-19 431 #define vgpu_vreg_t(vgpu, reg) \
90551a129 Zhenyu Wang 2017-12-19 432 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
90551a129 Zhenyu Wang 2017-12-19 433 #define vgpu_vreg(vgpu, offset) \
90551a129 Zhenyu Wang 2017-12-19 @434 (*(u32 *)(vgpu->mmio.vreg + (offset)))
90551a129 Zhenyu Wang 2017-12-19 435 #define vgpu_vreg64_t(vgpu, reg) \
90551a129 Zhenyu Wang 2017-12-19 436 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
90551a129 Zhenyu Wang 2017-12-19 437 #define vgpu_vreg64(vgpu, offset) \
90551a129 Zhenyu Wang 2017-12-19 438 (*(u64 *)(vgpu->mmio.vreg + (offset)))
90551a129 Zhenyu Wang 2017-12-19 439 #define vgpu_sreg_t(vgpu, reg) \
90551a129 Zhenyu Wang 2017-12-19 440 (*(u32 *)(vgpu->mmio.sreg + i915_mmio_reg_offset(reg)))
90551a129 Zhenyu Wang 2017-12-19 441 #define vgpu_sreg(vgpu, offset) \
90551a129 Zhenyu Wang 2017-12-19 442 (*(u32 *)(vgpu->mmio.sreg + (offset)))
82d375d1b Zhi Wang 2016-07-05 443
82d375d1b Zhi Wang 2016-07-05 444 #define for_each_active_vgpu(gvt, vgpu, id) \
82d375d1b Zhi Wang 2016-07-05 445 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
82d375d1b Zhi Wang 2016-07-05 446 for_each_if(vgpu->active)
82d375d1b Zhi Wang 2016-07-05 447
82d375d1b Zhi Wang 2016-07-05 448 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
82d375d1b Zhi Wang 2016-07-05 449 u32 offset, u32 val, bool low)
82d375d1b Zhi Wang 2016-07-05 450 {
82d375d1b Zhi Wang 2016-07-05 451 u32 *pval;
82d375d1b Zhi Wang 2016-07-05 452
82d375d1b Zhi Wang 2016-07-05 453 /* BAR offset should be 32 bits algiend */
82d375d1b Zhi Wang 2016-07-05 454 offset = rounddown(offset, 4);
82d375d1b Zhi Wang 2016-07-05 455 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
82d375d1b Zhi Wang 2016-07-05 456
82d375d1b Zhi Wang 2016-07-05 457 if (low) {
82d375d1b Zhi Wang 2016-07-05 458 /*
82d375d1b Zhi Wang 2016-07-05 459 * only update bit 31 - bit 4,
82d375d1b Zhi Wang 2016-07-05 460 * leave the bit 3 - bit 0 unchanged.
82d375d1b Zhi Wang 2016-07-05 461 */
82d375d1b Zhi Wang 2016-07-05 462 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
550dd77eb Xiaoguang Chen 2016-11-24 463 } else {
550dd77eb Xiaoguang Chen 2016-11-24 464 *pval = val;
82d375d1b Zhi Wang 2016-07-05 465 }
82d375d1b Zhi Wang 2016-07-05 466 }
82d375d1b Zhi Wang 2016-07-05 467
1f31c8294 Zhenyu Wang 2016-11-03 468 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
1f31c8294 Zhenyu Wang 2016-11-03 469 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
82d375d1b Zhi Wang 2016-07-05 470
afe04fbe6 Ping Gao 2017-03-30 471 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
afe04fbe6 Ping Gao 2017-03-30 472 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
1f31c8294 Zhenyu Wang 2016-11-03 473 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
1f31c8294 Zhenyu Wang 2016-11-03 474 struct intel_vgpu_type *type);
82d375d1b Zhi Wang 2016-07-05 475 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
cfe65f403 Changbin Du 2017-01-13 476 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
cfe65f403 Changbin Du 2017-01-13 477 unsigned int engine_mask);
9ec1e66b8 Jike Song 2016-11-03 478 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
b79c52aef Zhi Wang 2017-03-30 479 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
b79c52aef Zhi Wang 2017-03-30 480 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
1f31c8294 Zhenyu Wang 2016-11-03 481
2707e4446 Zhi Wang 2016-03-28 482 /* validating GM functions */
2707e4446 Zhi Wang 2016-03-28 483 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \
0c56d7a44 Yulei Zhang 2017-05-27 @484 ((gmadr >= vgpu_guest_aperture_gmadr_base(vgpu)) && \
0c56d7a44 Yulei Zhang 2017-05-27 @485 (gmadr <= vgpu_guest_aperture_gmadr_end(vgpu)))
2707e4446 Zhi Wang 2016-03-28 486
2707e4446 Zhi Wang 2016-03-28 487 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \
0c56d7a44 Yulei Zhang 2017-05-27 @488 ((gmadr >= vgpu_guest_hidden_gmadr_base(vgpu)) && \
0c56d7a44 Yulei Zhang 2017-05-27 @489 (gmadr <= vgpu_guest_hidden_gmadr_end(vgpu)))
2707e4446 Zhi Wang 2016-03-28 490
2707e4446 Zhi Wang 2016-03-28 491 #define vgpu_gmadr_is_valid(vgpu, gmadr) \
2707e4446 Zhi Wang 2016-03-28 @492 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
2707e4446 Zhi Wang 2016-03-28 @493 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
2707e4446 Zhi Wang 2016-03-28 494
:::::: The code at line 434 was first introduced by commit
:::::: 90551a1296d4dbe0dccc4c3cb5e57e7f2c929009 drm/i915/gvt: cleanup usage for typed mmio reg vs. offset
:::::: TO: Zhenyu Wang <zhenyuw at linux.intel.com>
:::::: CC: Zhenyu Wang <zhenyuw at linux.intel.com>
---
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https://lists.01.org/pipermail/kbuild-all Intel Corporation
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