[intel-gvt-linux:topic/gvt-xengt 23/31] drivers/gpu/drm/i915/gvt/vgpu.c:498:14: note: in expansion of macro 'vgpu_vreg'
kbuild test robot
fengguang.wu at intel.com
Mon Dec 25 13:37:30 UTC 2017
tree: https://github.com/intel/gvt-linux topic/gvt-xengt
head: 9cac0922ebda9b50c7c2736edd7b942d75bd4fea
commit: d796463e4185b0bf1d0ea67fd1fca6c13e91dec9 [23/31] drm/i915/gvt: Align the guest gm aperture start offset for live migration
config: x86_64-randconfig-s1-12251841 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout d796463e4185b0bf1d0ea67fd1fca6c13e91dec9
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/gvt/vgpu.c:35:0:
drivers/gpu/drm/i915/gvt/vgpu.c: In function 'intel_gvt_reset_vgpu_locked':
drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
>> drivers/gpu/drm/i915/gvt/vgpu.c:498:14: note: in expansion of macro 'vgpu_vreg'
u64 maddr = vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base));
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/vgpu.c:499:16: note: in expansion of macro 'vgpu_vreg'
u64 unmaddr = vgpu_vreg(vgpu,
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/vgpu.c:533:3: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:434:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/vgpu.c:535:3: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
^~~~~~~~~
vim +/vgpu_vreg +498 drivers/gpu/drm/i915/gvt/vgpu.c
464
465 /**
466 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
467 * @vgpu: virtual GPU
468 * @dmlr: vGPU Device Model Level Reset or GT Reset
469 * @engine_mask: engines to reset for GT reset
470 *
471 * This function is called when user wants to reset a virtual GPU through
472 * device model reset or GT reset. The caller should hold the gvt lock.
473 *
474 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
475 * the whole vGPU to default state as when it is created. This vGPU function
476 * is required both for functionary and security concerns.The ultimate goal
477 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
478 * assign a vGPU to a virtual machine we must isse such reset first.
479 *
480 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
481 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
482 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
483 * the reset request. Guest driver can issue a GT reset by programming the
484 * virtual GDRST register to reset specific virtual GPU engine or all
485 * engines.
486 *
487 * The parameter dev_level is to identify if we will do DMLR or GT reset.
488 * The parameter engine_mask is to specific the engines that need to be
489 * resetted. If value ALL_ENGINES is given for engine_mask, it means
490 * the caller requests a full GT reset that we will reset all virtual
491 * GPU engines. For FLR, engine_mask is ignored.
492 */
493 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
494 unsigned int engine_mask)
495 {
496 struct intel_gvt *gvt = vgpu->gvt;
497 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
> 498 u64 maddr = vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base));
499 u64 unmaddr = vgpu_vreg(vgpu,
500 vgtif_reg(avail_rs.nonmappable_gmadr.base));
501 unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
502
503 gvt_dbg_core("------------------------------------------\n");
504 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
505 vgpu->id, dmlr, engine_mask);
506
507 vgpu->resetting_eng = resetting_eng;
508
509 intel_vgpu_stop_schedule(vgpu);
510 /*
511 * The current_vgpu will set to NULL after stopping the
512 * scheduler when the reset is triggered by current vgpu.
513 */
514 if (scheduler->current_vgpu == NULL) {
515 mutex_unlock(&gvt->lock);
516 intel_gvt_wait_vgpu_idle(vgpu);
517 mutex_lock(&gvt->lock);
518 }
519
520 intel_vgpu_reset_submission(vgpu, resetting_eng);
521 /* full GPU reset or device model level reset */
522 if (engine_mask == ALL_ENGINES || dmlr) {
523 intel_vgpu_select_submission_ops(vgpu, 0);
524
525 /*fence will not be reset during virtual reset */
526 if (dmlr) {
527 intel_vgpu_reset_gtt(vgpu);
528 intel_vgpu_reset_resource(vgpu);
529 }
530
531 intel_vgpu_reset_mmio(vgpu, dmlr);
532 populate_pvinfo_page(vgpu);
533 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
534 maddr;
535 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
536 unmaddr;
537 intel_vgpu_reset_display(vgpu);
538
539 if (dmlr) {
540 intel_vgpu_reset_cfg_space(vgpu);
541 /* only reset the failsafe mode when dmlr reset */
542 vgpu->failsafe = false;
543 vgpu->pv_notified = false;
544 }
545 }
546
547 vgpu->resetting_eng = 0;
548 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
549 gvt_dbg_core("------------------------------------------\n");
550 }
551
---
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