[intel-gvt-linux:topic/gvt-xengt 25/31] drivers/gpu/drm/i915/gvt/migrate.c:427:26: error: implicit declaration of function 'INTEL_GVT_MMIO_OFFSET'
kbuild test robot
fengguang.wu at intel.com
Mon Dec 25 14:32:56 UTC 2017
tree: https://github.com/intel/gvt-linux topic/gvt-xengt
head: 9cac0922ebda9b50c7c2736edd7b942d75bd4fea
commit: 5a303d32d3afa3e8d426b03a0b684bbfe50cb10f [25/31] drm/i915/gvt: Implement vGPU status save and restore through new VFIO subregion VFIO_REGION_SUBTYPE_DEVICE_STATE
config: x86_64-randconfig-s1-12251841 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout 5a303d32d3afa3e8d426b03a0b684bbfe50cb10f
# save the attached .config to linux build tree
make ARCH=x86_64
All error/warnings (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/gvt/migrate.c:29:0:
drivers/gpu/drm/i915/gvt/migrate.c: In function 'vreg_load':
>> drivers/gpu/drm/i915/gvt/migrate.c:427:26: error: implicit declaration of function 'INTEL_GVT_MMIO_OFFSET' [-Werror=implicit-function-declaration]
MIG_VREG_RESTORE(vgpu, INTEL_GVT_MMIO_OFFSET(PIPECONF(pipe)));
^
drivers/gpu/drm/i915/gvt/gvt.h:435:31: note: in definition of macro 'vgpu_vreg'
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:427:3: note: in expansion of macro 'MIG_VREG_RESTORE'
MIG_VREG_RESTORE(vgpu, INTEL_GVT_MMIO_OFFSET(PIPECONF(pipe)));
^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/migrate.c: In function 'vggtt_save':
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:399:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:537:24: note: in expansion of macro 'vgpu_guest_aperture_offset'
u64 aperture_offset = vgpu_guest_aperture_offset(vgpu);
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:401:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:539:25: note: in expansion of macro 'vgpu_guest_hidden_offset'
u64 hidden_gm_offset = vgpu_guest_hidden_offset(vgpu);
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/migrate.c: In function 'vggtt_load':
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:399:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/migrate.c:589:29: note: in expansion of macro 'vgpu_guest_aperture_offset'
u64 dest_aperture_offset = vgpu_guest_aperture_offset(vgpu);
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:401:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/migrate.c:591:30: note: in expansion of macro 'vgpu_guest_hidden_offset'
u64 dest_hidden_gm_offset = vgpu_guest_hidden_offset(vgpu);
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:399:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:403:47: note: in expansion of macro 'vgpu_guest_aperture_offset'
#define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:487:13: note: in expansion of macro 'vgpu_guest_aperture_gmadr_base'
((gmadr >= vgpu_guest_aperture_gmadr_base(vgpu)) && \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:495:5: note: in expansion of macro 'vgpu_gmadr_is_aperture'
((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:623:7: note: in expansion of macro 'vgpu_gmadr_is_valid'
if (vgpu_gmadr_is_valid(vgpu, ggtt_index << I915_GTT_PAGE_SHIFT)) {
^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:399:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:403:47: note: in expansion of macro 'vgpu_guest_aperture_offset'
#define vgpu_guest_aperture_gmadr_base(vgpu) (vgpu_guest_aperture_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:405:3: note: in expansion of macro 'vgpu_guest_aperture_gmadr_base'
(vgpu_guest_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:488:13: note: in expansion of macro 'vgpu_guest_aperture_gmadr_end'
(gmadr <= vgpu_guest_aperture_gmadr_end(vgpu)))
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:495:5: note: in expansion of macro 'vgpu_gmadr_is_aperture'
((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:623:7: note: in expansion of macro 'vgpu_gmadr_is_valid'
if (vgpu_gmadr_is_valid(vgpu, ggtt_index << I915_GTT_PAGE_SHIFT)) {
^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:401:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:407:45: note: in expansion of macro 'vgpu_guest_hidden_offset'
#define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:491:13: note: in expansion of macro 'vgpu_guest_hidden_gmadr_base'
((gmadr >= vgpu_guest_hidden_gmadr_base(vgpu)) && \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:496:5: note: in expansion of macro 'vgpu_gmadr_is_hidden'
(vgpu_gmadr_is_hidden(vgpu, gmadr))))
^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:623:7: note: in expansion of macro 'vgpu_gmadr_is_valid'
if (vgpu_gmadr_is_valid(vgpu, ggtt_index << I915_GTT_PAGE_SHIFT)) {
^~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:435:28: error: invalid operands to binary + (have 'void *' and 'i915_reg_t {aka const struct <anonymous>}')
(*(u32 *)(vgpu->mmio.vreg + (offset)))
^
drivers/gpu/drm/i915/gvt/gvt.h:401:2: note: in expansion of macro 'vgpu_vreg'
vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base))
^~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:407:45: note: in expansion of macro 'vgpu_guest_hidden_offset'
#define vgpu_guest_hidden_gmadr_base(vgpu) (vgpu_guest_hidden_offset(vgpu))
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:409:3: note: in expansion of macro 'vgpu_guest_hidden_gmadr_base'
(vgpu_guest_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:492:13: note: in expansion of macro 'vgpu_guest_hidden_gmadr_end'
(gmadr <= vgpu_guest_hidden_gmadr_end(vgpu)))
^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/gvt/gvt.h:496:5: note: in expansion of macro 'vgpu_gmadr_is_hidden'
(vgpu_gmadr_is_hidden(vgpu, gmadr))))
^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/gvt/migrate.c:623:7: note: in expansion of macro 'vgpu_gmadr_is_valid'
if (vgpu_gmadr_is_valid(vgpu, ggtt_index << I915_GTT_PAGE_SHIFT)) {
^~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/INTEL_GVT_MMIO_OFFSET +427 drivers/gpu/drm/i915/gvt/migrate.c
405
406 static int vreg_load(const struct gvt_migration_obj_t *obj, u32 size)
407 {
408 struct intel_vgpu *vgpu = (struct intel_vgpu *) obj->vgpu;
409 void *dest = vgpu->mmio.vreg;
410 int n_transfer = INV;
411 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
412 enum pipe pipe;
413
414 if (unlikely(size != obj->region.size)) {
415 gvt_err("migration obj size isn't match between target and image!"
416 " memsize=%d imgsize=%d\n",
417 obj->region.size,
418 size);
419 return n_transfer;
420 } else {
421 n_transfer = obj->region.size;
422 memcpy(dest, obj->img + obj->offset, n_transfer);
423 }
424
425 //restore vblank emulation
426 for (pipe = PIPE_A; pipe < I915_MAX_PIPES; ++pipe)
> 427 MIG_VREG_RESTORE(vgpu, INTEL_GVT_MMIO_OFFSET(PIPECONF(pipe)));
428
429 return n_transfer;
430 }
431
432 static int workload_save(const struct gvt_migration_obj_t *obj)
433 {
434 struct intel_vgpu *vgpu = (struct intel_vgpu *) obj->vgpu;
435 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
436 struct gvt_region_t region;
437 struct intel_engine_cs *engine;
438 struct intel_vgpu_workload *pos, *n;
439 unsigned int i;
440 struct gvt_pending_workload_t workload;
441 void *des = obj->img + obj->offset;
442 unsigned int num = 0;
443 u32 sz = sizeof(struct gvt_pending_workload_t);
444
445 for_each_engine(engine, dev_priv, i) {
446 list_for_each_entry_safe(pos, n,
447 &vgpu->submission.workload_q_head[engine->id], list) {
448 workload.ring_id = pos->ring_id;
449 memcpy(&workload.elsp_dwords, &pos->elsp_dwords,
450 sizeof(struct intel_vgpu_elsp_dwords));
451 memcpy(des + sizeof(struct gvt_region_t) + (num * sz),
452 &workload, sz);
453 num++;
454 }
455 }
456
457 region.type = GVT_MIGRATION_WORKLOAD;
458 region.size = num * sz;
459 memcpy(des, ®ion, sizeof(struct gvt_region_t));
460
461 return sizeof(struct gvt_region_t) + region.size;
462 }
463
464 static int workload_load(const struct gvt_migration_obj_t *obj, u32 size)
465 {
466 struct intel_vgpu *vgpu = (struct intel_vgpu *) obj->vgpu;
467 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
468 int n_transfer = INV;
469 struct gvt_pending_workload_t workload;
470 struct intel_engine_cs *engine;
471 void *src = obj->img + obj->offset;
472 u64 pa, off;
473 u32 sz = sizeof(struct gvt_pending_workload_t);
474 int i, j;
475
476 if (size == 0)
477 return size;
478
479 if (unlikely(size % sz) != 0) {
480 gvt_err("migration obj size isn't match between target and image!"
481 " memsize=%d imgsize=%d\n",
482 obj->region.size,
483 size);
484 return n_transfer;
485 }
486
487 for (i = 0; i < size / sz; i++) {
488 memcpy(&workload, src + (i * sz), sz);
489 engine = dev_priv->engine[workload.ring_id];
490 off = i915_mmio_reg_offset(RING_ELSP(engine));
491 pa = intel_vgpu_mmio_offset_to_gpa(vgpu, off);
492 for (j = 0; j < 4; j++) {
493 intel_vgpu_emulate_mmio_write(vgpu, pa,
494 &workload.elsp_dwords.data[j], 4);
495 }
496 }
497
498 n_transfer = size;
499
500 return n_transfer;
501 }
502
503 static int
504 mig_ggtt_save_restore(struct intel_vgpu_mm *ggtt_mm,
505 void *data, u64 gm_offset,
506 u64 gm_sz,
507 bool save_to_image)
508 {
509 struct intel_vgpu *vgpu = ggtt_mm->vgpu;
510 struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
511
512 void *ptable;
513 int sz;
514 int shift = vgpu->gvt->device_info.gtt_entry_size_shift;
515
516 ptable = ggtt_mm->virtual_page_table +
517 (gma_ops->gma_to_ggtt_pte_index(gm_offset) << shift);
518 sz = (gm_sz >> I915_GTT_PAGE_SHIFT) << shift;
519
520 if (save_to_image)
521 memcpy(data, ptable, sz);
522 else
523 memcpy(ptable, data, sz);
524
525 return sz;
526 }
527
528 static int vggtt_save(const struct gvt_migration_obj_t *obj)
529 {
530 int ret = INV;
531 struct intel_vgpu *vgpu = (struct intel_vgpu *) obj->vgpu;
532 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
533 void *des = obj->img + obj->offset;
534 struct gvt_region_t region;
535 int sz;
536
> 537 u64 aperture_offset = vgpu_guest_aperture_offset(vgpu);
538 u64 aperture_sz = vgpu_aperture_sz(vgpu);
> 539 u64 hidden_gm_offset = vgpu_guest_hidden_offset(vgpu);
540 u64 hidden_gm_sz = vgpu_hidden_sz(vgpu);
541
542 des += sizeof(struct gvt_region_t);
543
544 /*TODO:512MB GTT takes total 1024KB page table size, optimization here*/
545
546 gvt_dbg_core("Guest aperture=0x%llx (HW: 0x%llx),"
547 "Guest Hidden=0x%llx (HW:0x%llx)\n",
548 aperture_offset, vgpu_aperture_offset(vgpu),
549 hidden_gm_offset, vgpu_hidden_offset(vgpu));
550
551 /*TODO:to be fixed after removal of address ballooning */
552 ret = 0;
553
554 /* aperture */
555 sz = mig_ggtt_save_restore(ggtt_mm, des,
556 aperture_offset, aperture_sz, true);
557 des += sz;
558 ret += sz;
559
560 /* hidden gm */
561 sz = mig_ggtt_save_restore(ggtt_mm, des,
562 hidden_gm_offset, hidden_gm_sz, true);
563 des += sz;
564 ret += sz;
565
566 /* Save the total size of this session */
567 region.type = GVT_MIGRATION_GTT;
568 region.size = ret;
569 memcpy(obj->img + obj->offset, ®ion, sizeof(struct gvt_region_t));
570
571 ret += sizeof(struct gvt_region_t);
572
573 return ret;
574 }
575
576 static int vggtt_load(const struct gvt_migration_obj_t *obj, u32 size)
577 {
578 int ret;
579 u32 ggtt_index;
580 void *src;
581 int sz;
582
583 struct intel_vgpu *vgpu = (struct intel_vgpu *) obj->vgpu;
584 struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
585
586 int shift = vgpu->gvt->device_info.gtt_entry_size_shift;
587
588 /* offset to bar1 beginning */
589 u64 dest_aperture_offset = vgpu_guest_aperture_offset(vgpu);
590 u64 aperture_sz = vgpu_aperture_sz(vgpu);
591 u64 dest_hidden_gm_offset = vgpu_guest_hidden_offset(vgpu);
592 u64 hidden_gm_sz = vgpu_hidden_sz(vgpu);
593
594 gvt_dbg_core("Guest aperture=0x%llx (HW: 0x%llx),"
595 "Guest Hidden=0x%llx (HW:0x%llx)\n",
596 dest_aperture_offset, vgpu_aperture_offset(vgpu),
597 dest_hidden_gm_offset, vgpu_hidden_offset(vgpu));
598
599 if ((size>>shift) !=
600 ((aperture_sz + hidden_gm_sz) >> I915_GTT_PAGE_SHIFT)) {
601 gvt_err("ggtt restore failed due to page table size not match\n");
602 return INV;
603 }
604
605 ret = 0;
606 src = obj->img + obj->offset;
607
608 /* aperture */
609 sz = mig_ggtt_save_restore(ggtt_mm,
610 src, dest_aperture_offset, aperture_sz, false);
611 src += sz;
612 ret += sz;
613
614 /* hidden GM */
615 sz = mig_ggtt_save_restore(ggtt_mm, src,
616 dest_hidden_gm_offset, hidden_gm_sz, false);
617 ret += sz;
618
619 /* aperture/hidden GTT emulation from Source to Target */
620 for (ggtt_index = 0; ggtt_index < ggtt_mm->page_table_entry_cnt;
621 ggtt_index++) {
622
> 623 if (vgpu_gmadr_is_valid(vgpu, ggtt_index << I915_GTT_PAGE_SHIFT)) {
624 struct intel_gvt_gtt_pte_ops *ops =
625 vgpu->gvt->gtt.pte_ops;
626 struct intel_gvt_gtt_entry e;
627 u64 offset;
628 u64 pa;
629
630 /* TODO: hardcode to 64bit right now */
631 offset = vgpu->gvt->device_info.gtt_start_offset
632 + (ggtt_index<<shift);
633
634 pa = intel_vgpu_mmio_offset_to_gpa(vgpu, offset);
635
636 /* read out virtual GTT entity and
637 * trigger emulate write
638 */
639 ggtt_get_guest_entry(ggtt_mm, &e, ggtt_index);
640 if (ops->test_present(&e)) {
641 /* same as gtt_emulate
642 * _write(vgt, offset, &e.val64, 1<<shift);
643 * Using vgt_emulate_write as to align with vReg load
644 */
645 intel_vgpu_emulate_mmio_write(vgpu, pa,
646 &e.val64, 1<<shift);
647 }
648 }
649 }
650
651 return ret;
652 }
653
---
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