[Intel-xe] [PATCH] drm/xe: fix HuC FW ordering for DG1

[Lucas De Marchi]

On Tue, Jun 27, 2023 at 03:28:56PM -0700, Daniele Ceraolo Spurio wrote:
>The firmware definitions must be ordered based on platform, from newer
>to older, which means that the DG1 FW must come before the ADL one.
>
>References: https://gitlab.freedesktop.org/drm/intel/-/issues/8699

humn... how is that going to fix that?? Also "from newer to older" means
the value follows enum xe_platform

/*                                                                               
  * Keep this in graphics version based order and chronological order within a    
  * version                                                                       
  */                                                                              
enum xe_platform {                                                               
         XE_PLATFORM_UNINITIALIZED = 0,                                           
         XE_TIGERLAKE,                                                            
         XE_ROCKETLAKE,                                                           
         XE_ALDERLAKE_S,                                                          
         XE_ALDERLAKE_P,                                                          
         XE_ALDERLAKE_N,                                                          
         XE_DG1,                                                                  
         XE_DG2,                                                                  
         XE_PVC,                                                                  
         XE_METEORLAKE,                                                           
};

Since DG1 is 12.1, it was decided to leave it after ADL.

Note that all of this in xe is currently just a convention, not a
requirement.

also very weird to have xe_huc_copy running on drm-tip if xe driver is
not merged in drm-tip.

Lucas De Marchi

>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>---
> drivers/gpu/drm/xe/xe_uc_fw.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>index b05038921e02..1aa9a4925574 100644
>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>@@ -111,9 +111,9 @@ struct fw_blobs_by_type {
> 	fw_def(TIGERLAKE,	major_ver(i915,	guc,	tgl,	70, 5))
>
> #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver)				\
>+	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\
> 	fw_def(ALDERLAKE_P,	no_ver(i915,	huc,	tgl))			\
> 	fw_def(ALDERLAKE_S,	no_ver(i915,	huc,	tgl))			\
>-	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\
> 	fw_def(ROCKETLAKE,	no_ver(i915,	huc,	tgl))			\
> 	fw_def(TIGERLAKE,	no_ver(i915,	huc,	tgl))
>
>-- 
>2.41.0
>