[Intel-xe] [PATCH] drm/xe: fix HuC FW ordering for DG1

[Lucas De Marchi]

On Thu, Jun 29, 2023 at 12:49:55AM -0300, Lucas De Marchi wrote:
>On Tue, Jun 27, 2023 at 03:28:56PM -0700, Daniele Ceraolo Spurio wrote:
>>The firmware definitions must be ordered based on platform, from newer
>>to older, which means that the DG1 FW must come before the ADL one.
>>
>>References: https://gitlab.freedesktop.org/drm/intel/-/issues/8699
>
>humn... how is that going to fix that?? Also "from newer to older" means
>the value follows enum xe_platform
>
>/*                                                                                
>* Keep this in graphics version based order and chronological order 
>within a     * version                                                                        
>*/                                                                              
>enum xe_platform {                                                                       
>XE_PLATFORM_UNINITIALIZED = 0,                                                   
>XE_TIGERLAKE,                                                                    
>XE_ROCKETLAKE,                                                                   
>XE_ALDERLAKE_S,                                                                  
>XE_ALDERLAKE_P,                                                                  
>XE_ALDERLAKE_N,                                                                  
>XE_DG1,                                                                          
>XE_DG2,                                                                          
>XE_PVC,                                                                          
>XE_METEORLAKE,                                                           
>};
>
>Since DG1 is 12.1, it was decided to leave it after ADL.
>
>Note that all of this in xe is currently just a convention, not a
>requirement.

well... I misread the diff, it's actually making it the right order,
which is the inverse of the one above, so looks good.

>
>also very weird to have xe_huc_copy running on drm-tip if xe driver is
>not merged in drm-tip.

even though the link is to drm-tip/, it's actually the xe driver indeed:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9200/bat-dg1-8/boot0.txt
<5>[    0.000000] Linux version 6.3.0-xe (root at fd52a587a960) (gcc (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #1 SMP PREEMPT_DYNAMIC Fri Jun 16 21:26:39 UTC 2023

So everything here looks good. Sorry for the noise.

Lucas De Marchi

>
>Lucas De Marchi
>
>>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
>>---
>>drivers/gpu/drm/xe/xe_uc_fw.c | 2 +-
>>1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>>index b05038921e02..1aa9a4925574 100644
>>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>>@@ -111,9 +111,9 @@ struct fw_blobs_by_type {
>>	fw_def(TIGERLAKE,	major_ver(i915,	guc,	tgl,	70, 5))
>>
>>#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver)				\
>>+	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\
>>	fw_def(ALDERLAKE_P,	no_ver(i915,	huc,	tgl))			\
>>	fw_def(ALDERLAKE_S,	no_ver(i915,	huc,	tgl))			\
>>-	fw_def(DG1,		no_ver(i915,	huc,	dg1))			\
>>	fw_def(ROCKETLAKE,	no_ver(i915,	huc,	tgl))			\
>>	fw_def(TIGERLAKE,	no_ver(i915,	huc,	tgl))
>>
>>-- 
>>2.41.0
>>