[PATCH 3/3] drm/xe/xelp: Add Wa_18022495364

[Matt Roper]

On Tue, May 27, 2025 at 02:05:02PM -0500, Lucas De Marchi wrote:
> On Fri, May 16, 2025 at 12:06:50PM -0700, Matt Roper wrote:
> > On Fri, May 16, 2025 at 08:44:12AM +0100, Tvrtko Ursulin wrote:
> > > Add Wa_18022495364 as a context indirect workaround.
> > > 
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
> > > ---
> > >  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  3 +++
> > >  drivers/gpu/drm/xe/xe_lrc.c              | 12 ++++++++++++
> > >  drivers/gpu/drm/xe/xe_wa_oob.rules       |  1 +
> > >  3 files changed, 16 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > index d1d2592e010d..94d778d5425d 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > @@ -112,6 +112,9 @@
> > >  #define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
> > >  #define   CS_PRIORITY_MEM_READ			REG_BIT(7)
> > > 
> > > +#define CS_DEBUG_MODE2(base)			XE_REG((base) + 0xd8, XE_REG_OPTION_MASKED)
> > > +#define   INSTRUCTION_STATE_CACHE_INVALIDATE	REG_BIT(6)
> > > +
> > >  #define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
> > >  #define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> > > index 6022068ce6b6..9a07fc6d78ab 100644
> > > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > > @@ -1028,6 +1028,15 @@ xelp_emit_cmd_buf_wa(struct xe_lrc *lrc, u32 *cmd)
> > >  	return cmd;
> > >  }
> > > 
> > > +static u32 *xelp_invalidate_state_cache(u32 *cmd)
> > > +{
> > > +	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);
> > > +	*cmd++ = CS_DEBUG_MODE1(0).addr;
> > > +	*cmd++ = _MASKED_BIT_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
> > > +
> > > +	return cmd;
> > > +}
> > > +
> > >  static u32 *
> > >  xelp_setup_indirect_ctx_rcs(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> > >  			    u32 *cmd)
> > > @@ -1037,6 +1046,9 @@ xelp_setup_indirect_ctx_rcs(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
> > >  	cmd = xelp_emit_cmd_buf_wa(lrc, cmd);
> > >  	cmd = xelp_emit_restore_scratch(lrc, cmd);
> > > 
> > > +	if (XE_WA(lrc->gt, 18022495364))
> > > +		cmd = xelp_invalidate_state_cache(cmd);
> > 
> > This is another one where the official workaround description asks us to
> > use the per-context workaround bb rather than the indirect context
> > workaround bb.  This register is already part of the LRC, so which batch
> > buffer gets used determines whether this extra write will happen before
> > or after the standard write that would have been part of the LRC
> > restore; I'm not sure if that matters or not from a functional
> > perspective.
> 
> Does it really matter considering this is a masked register? Doesn't
> that mean it could just be implemented as an LRC workaround ?

No, I believe this register bit is a "trigger side effect immediately at
time of writing" bit so the goal here isn't to just get the value into
the register in general, but to actually (re)write that bit an
additional time during the context restore.

Reading the internal details that aren't in the final workaround text,
it sounds like the underlying issue this workaround is avoiding is some
kind of race between RCS and POCS.  So in that case it seems like the
whole workaround probably isn't actually important on Linux where POSH
and the POCS command streamer are never used.  


Matt

> 
> Lucas De Marchi
> 
> > 
> > 
> > Matt
> > 
> > > +
> > >  	return cmd;
> > >  }
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > index 9efc5accd43d..a32f5ee9e917 100644
> > > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > @@ -1,4 +1,5 @@
> > >  1607983814	GRAPHICS_VERSION_RANGE(1200, 1210)
> > > +18022495364	GRAPHICS_VERSION_RANGE(1200, 1210)
> > >  22012773006	GRAPHICS_VERSION_RANGE(1200, 1250)
> > >  14014475959	GRAPHICS_VERSION_RANGE(1270, 1271), GRAPHICS_STEP(A0, B0)
> > >  		PLATFORM(DG2)
> > > --
> > > 2.48.0
> > > 
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation