[PATCH 3/3] drm/xe/bmg: Update Wa_16023588340
Matthew Auld
matthew.auld at intel.com
Fri May 30 08:49:41 UTC 2025
On 30/05/2025 09:20, Vinay Belgaumkar wrote:
> This allows for additional L2 caching modes.
>
> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>
> Cc: Matthew Auld <matthew.auld at intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> ---
> drivers/gpu/drm/xe/xe_gt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 0e5d243c9451..6c4cb9576fb6 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -118,7 +118,7 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
> xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
> }
>
> - xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
> + xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF);
> xe_force_wake_put(gt_to_fw(gt), fw_ref);
> }
>
More information about the Intel-xe
mailing list