Mesa (staging/19.2): ac: add radeon_info::tcc_harvested

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Module: Mesa
Branch: staging/19.2
Commit: 33eecbcc9bdf197a82477d01e4aa3c1d853bc392
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=33eecbcc9bdf197a82477d01e4aa3c1d853bc392

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Sep 24 16:56:21 2019 -0400

ac: add radeon_info::tcc_harvested

Cc: 19.2 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 8cbe83445b2ec78fab1f303918c79268713500b5)
Conflicts resolved by Dylan Baker

Conflicts:
	src/amd/common/ac_gpu_info.h

---

 src/amd/common/ac_gpu_info.c | 4 ++++
 src/amd/common/ac_gpu_info.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 425330bcb28..86c27f413da 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -427,6 +427,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 	}
 	if (info->chip_class >= GFX10) {
 		info->tcc_cache_line_size = 128;
+		/* This is a hack, but it's all we can do without a kernel upgrade. */
+		info->tcc_harvested =
+			(info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
 	} else {
 		info->tcc_cache_line_size = 64;
 	}
@@ -548,6 +551,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
 	printf("    clock_crystal_freq = %i\n", info->clock_crystal_freq);
 	printf("    tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+	printf("    tcc_harvested = %u\n", info->tcc_harvested);
 
 	printf("    use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
 	printf("    use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index a3a187e2245..40dcdf385c9 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -58,6 +58,7 @@ struct radeon_info {
 	uint32_t                    num_sdma_rings;
 	uint32_t                    clock_crystal_freq;
 	uint32_t                    tcc_cache_line_size;
+	bool			    tcc_harvested;
 
 	/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
 	/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */