Mesa (main): radv: don't lower vectorized instructions to 32bit

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Module: Mesa
Branch: main
Commit: 4235dd7b47286919fdd7f0c9dfad6e4055d9fb1f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4235dd7b47286919fdd7f0c9dfad6e4055d9fb1f

Author: Daniel Schürmann <daniel at schuermann.dev>
Date:   Mon Jun 27 14:49:49 2022 +0200

radv: don't lower vectorized instructions to 32bit

Reviewed-by: Georg Lehmann <dadschoorse at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>

---

 src/amd/vulkan/radv_pipeline.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d22314c49fa..68380cbedbd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3990,6 +3990,11 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
       return 0;
    nir_alu_instr *alu = nir_instr_as_alu(instr);
 
+   /* If an instruction is not scalarized by this point,
+    * it can be emitted as packed instruction */
+   if (alu->dest.dest.ssa.num_components > 1)
+      return 0;
+
    if (alu->dest.dest.ssa.bit_size & (8 | 16)) {
       unsigned bit_size = alu->dest.dest.ssa.bit_size;
       switch (alu->op) {