[Mesa-dev] [PATCH] i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.

[Eric Anholt]

On Thu, 18 Aug 2011 02:15:56 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
> Makes the new vertex shader backend work on Ivybridge.
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/i965/brw_eu_emit.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 27e8130..c5013de 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -2244,10 +2244,13 @@ void brw_urb_WRITE(struct brw_compile *p,
>  
>     if (intel->gen == 7) {
>        /* Enable Channel Masks in the URB_WRITE_HWORD message header */
> +      brw_push_insn_state(p);
> +      brw_set_access_mode(p, BRW_ALIGN_1);
>        brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
>  		       BRW_REGISTER_TYPE_UD),
>  	        retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
>  		brw_imm_ud(0xff00));
> +      brw_pop_insn_state(p);
>     }

Reviewed-by: Eric Anholt <eric at anholt.net>

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