[Mesa-dev] [PATCH 4/4] i965: Make sure VALIGN_4 surfaces are Y tiled

[Ben Widawsky]

Quoting the workaround already there:
"This field must be set to VALIGN_4 for all tiled Y Render Target surfaces."

This patch simply asserts we return Y tiled, instead of X or Y. It has no effect
on the code since the only caller already does the right thing. However, I think
it makes the workaround more understandable, and more future-proof.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 25bf37b..ceb7434 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -508,6 +508,9 @@ intel_miptree_choose_tiling(struct brw_context *brw,
    if (brw->gen >= 6 && mt->align_h == 2 &&
        brw->format_supported_as_render_target[format]) {
       return I915_TILING_X;
+   } else if (mt->align_h == 4 &&
+              brw->format_supported_as_render_target[format]) {
+      return I915_TILING_Y;
    }
 
    return I915_TILING_Y | I915_TILING_X;
-- 
2.1.3