[Mesa-dev] [PATCH 3/4] i965: Set VALIGN constraints for all gens >= 6

[Ben Widawsky]

As far as I can tell, this restriction is always needed.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index efe63b5..25bf37b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -505,7 +505,7 @@ intel_miptree_choose_tiling(struct brw_context *brw,
     * to know that ahead of time.  And besides, since we use a vertical
     * alignment of 4 as often as we can, this shouldn't happen very often.
     */
-   if (brw->gen == 7 && mt->align_h == 2 &&
+   if (brw->gen >= 6 && mt->align_h == 2 &&
        brw->format_supported_as_render_target[format]) {
       return I915_TILING_X;
    }
-- 
2.1.3