[Mesa-dev] [PATCH 08/17] i965/gen6 depth surface: calculate minimum array element being rendered

[Pohjolainen, Topi]

On Fri, Jul 18, 2014 at 02:16:43PM -0700, Jordan Justen wrote:
> (a23cfb8 for gen6)
> 
> In layered rendering this will be 0. Otherwise it will be the
> selected slice.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen6_blorp.cpp     |  3 +++
>  src/mesa/drivers/dri/i965/gen6_depth_state.c | 10 ++++++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index 131c4aa..ff1732d 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -793,6 +793,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>     uint32_t tile_mask_x, tile_mask_y;
>     uint32_t surftype;
>     unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
> +   unsigned int min_array_element;
>     GLenum gl_target = params->depth.mt->target;
>     unsigned int lod;
>  
> @@ -818,6 +819,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>                                     NULL,
>                                     &tile_mask_x, &tile_mask_y);
>  
> +   min_array_element = params->depth.layer;
> +
>     lod = params->depth.level - params->depth.mt->first_level;
>  
>     /* 3DSTATE_DEPTH_BUFFER */
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 8ee7c00..abb2124 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -48,6 +48,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>     struct gl_framebuffer *fb = ctx->DrawBuffer;
>     uint32_t surftype;
>     unsigned int depth = 1;
> +   unsigned int min_array_element;
>     GLenum gl_target = GL_TEXTURE_2D;
>     unsigned int lod;
>     const struct intel_renderbuffer *irb = NULL;
> @@ -100,6 +101,15 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>        break;
>     }
>  
> +   if (fb->MaxNumLayers > 0 || !irb) {
> +      min_array_element = 0;
> +   } else if (irb->mt->num_samples > 1) {
> +      /* Convert physical layer to logical layer. */
> +      min_array_element = irb->mt_layer / irb->mt->num_samples;

Above in gen6_blorp_emit_depth_stencil_config() you didn't try to adjust,
but here you do, why? In fact, checking the gen7 equivalent (patch a23cfb8),
I don't understand why the adjustment is done there either - even on gen7/8
both depth-msaa and stencil-msaa are still interleaved, right?

> +   } else {
> +      min_array_element = irb->mt_layer;
> +   }
> +
>     lod = irb ? irb->mt_level - irb->mt->first_level : 0;
>  
>     unsigned int len;
> -- 
> 2.0.1
> 
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