[Mesa-dev] [PATCH 16/17] i965/gen6: Stencil/hiz needs an offset for LOD > 0

[Pohjolainen, Topi]

On Fri, Jul 18, 2014 at 02:16:51PM -0700, Jordan Justen wrote:
> Since gen6 separate stencil & hiz only supports LOD0, we need to
> program an offset to the LOD when emitting the separate stencil/hiz.
> 
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/gen6_blorp.cpp     | 10 +++++++-
>  src/mesa/drivers/dri/i965/gen6_depth_state.c | 34 ++++++++++++++++++++++++++--
>  2 files changed, 41 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> index 5a56442..4dab569 100644
> --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
> @@ -871,13 +871,21 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
>     /* 3DSTATE_HIER_DEPTH_BUFFER */
>     {
>        struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
> +      uint32_t offset = 0;
> +
> +      if (hiz_mt->non_mip_arrays) {
> +         offset = intel_miptree_get_aligned_offset(hiz_mt,
> +                                                   hiz_mt->level[lod].level_x,
> +                                                   hiz_mt->level[lod].level_y,
> +                                                   false);
> +      }
>  
>        BEGIN_BATCH(3);
>        OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
>        OUT_BATCH(hiz_mt->pitch - 1);
>        OUT_RELOC(hiz_mt->bo,
>                  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> -                0);
> +                offset);
>        ADVANCE_BATCH();
>     }
>  
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index b58f970..fd37594 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -183,12 +183,22 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>        /* Emit hiz buffer. */
>        if (hiz) {
>           struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
> +         uint32_t offset = 0;
> +
> +         if (hiz_mt->non_mip_arrays) {
> +            offset = intel_miptree_get_aligned_offset(
> +                        hiz_mt,
> +                        hiz_mt->level[lod].level_x,
> +                        hiz_mt->level[lod].level_y,
> +                        false);
> +         }
> +
>  	 BEGIN_BATCH(3);
>  	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
>  	 OUT_BATCH(hiz_mt->pitch - 1);
>  	 OUT_RELOC(hiz_mt->bo,
>  		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> -		   0);
> +		   offset);
>  	 ADVANCE_BATCH();
>        } else {
>  	 BEGIN_BATCH(3);
> @@ -200,6 +210,26 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>  
>        /* Emit stencil buffer. */
>        if (separate_stencil) {
> +         uint32_t offset = 0;
> +
> +         if (stencil_mt->non_mip_arrays) {
> +            if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
> +               /* Note: we can't compute the stencil offset using
> +                * intel_region_get_aligned_offset(), because stencil_region
> +                * claims that the region is untiled even though it's W tiled.
> +                */
> +               offset =
> +                  stencil_mt->level[lod].level_y * stencil_mt->pitch +
> +                  stencil_mt->level[lod].level_x * 64;

As we don't have the stencil using the normal mip-level organization (array
of miptrees) but rather mip-tree of arrays, all the individual slices have
x-offset zero, right?

> +            } else {
> +               offset = intel_miptree_get_aligned_offset(
> +                           stencil_mt,
> +                           stencil_mt->level[lod].level_x,
> +                           stencil_mt->level[lod].level_y,
> +                           false);
> +            }
> +         }
> +
>  	 BEGIN_BATCH(3);
>  	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
>           /* The stencil buffer has quirky pitch requirements.  From Vol 2a,
> @@ -210,7 +240,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>  	 OUT_BATCH(2 * stencil_mt->pitch - 1);
>  	 OUT_RELOC(stencil_mt->bo,
>  		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> -		   0);
> +		   offset);
>  	 ADVANCE_BATCH();
>        } else {
>  	 BEGIN_BATCH(3);
> -- 
> 2.0.1
> 
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