[Mesa-dev] [PATCH 04/17] i965: Split gen6 depth hiz state out from brw
kenneth at whitecape.org
Wed Jul 23 12:18:12 PDT 2014
On Tuesday, July 22, 2014 11:53:16 AM Pohjolainen, Topi wrote:
> On Fri, Jul 18, 2014 at 02:16:39PM -0700, Jordan Justen wrote:
> > We will program the gen6 hiz depth state differently to enable layered
> > rendering on gen6.
> > v2:
> > * Remove unneeded gen6_emit_depthbuffer as suggested by Topi
> > Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> Compared side by side with brw_emit_depth_stencil_hiz() and looks identical.
> I was hoping we could start merging gen6-gen8 surface state logic as there
> seems to be quite a bit of overlap. This change adds even more but I think
> it is still a step forward as now gen6 is closer to gen7/8.
> Proper refactoring between different generations requires some more thinking
> and possibly some trial-and-error too. This patch will make that work easier
> in my opinion.
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
I'm really glad to see this split - I did something similar a long time ago, but it conflicted with Paul's other works, so I never landed it. Either that or I never quite got it working. :)
That said, you really should clean up both halves of the split: delete the Gen6 checks from brw_emit_depth_stencil_hiz, and delete the Gen4-5 checks from gen6_emit_depth_stencil_hiz. You could do that here, or in a patch or two immediately following the copy-and-paste.
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 819 bytes
Desc: This is a digitally signed message part.
More information about the mesa-dev