[Mesa-dev] [PATCH 05/22] i965/fs: Recompile when switching to/from stencil indexing

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_program.h | 20 ++++++++++++++++++++
 src/mesa/drivers/dri/i965/brw_wm.c      | 14 ++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_program.h b/src/mesa/drivers/dri/i965/brw_program.h
index a8650c3..561d2fe 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -55,6 +55,26 @@ struct brw_sampler_prog_key_data {
     * For Sandybridge, which shader w/a we need for gather quirks.
     */
    uint8_t gen6_gather_wa[MAX_SAMPLERS];
+
+   /**
+    * ARB_stencil_texturing on gen6/7 requires W-tiled surface to be configured
+    * as linear for the sampling engine, and then for the program to compensate
+    * for the difference in coordinates. In addition, the sampler engine on
+    * gen7 onwards does not understand the interleaved MSAA used in W-tiled
+    * buffers.
+    * This field is used in the compiler to know when to emit code for
+    * compensating for the difference in coordinates. Allowed values are
+    * zero, one, four and eight, value zero indicating no translation, one
+    * indicating tiling translation only (single sampled), and the latter two
+    * tiling translation with msaa encoding.
+    *
+    * In addition, as one cannot use the sampling engine to determine the
+    * correct mip-level offset either, the program needs to do it manually.
+    * Unfortunately it needs to know if the level-of-detail is w.r.t. the very
+    * beginning of the miptree or some level between.
+    */
+   uint8_t num_w_tiled_samples[MAX_SAMPLERS];
+   uint8_t w_tiled_base_level[MAX_SAMPLERS];
 };
 
 #ifdef __cplusplus
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index d716e6f..f9a39ad 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -226,6 +226,12 @@ brw_debug_recompile_sampler_key(struct brw_context *brw,
    for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
       found |= key_debug(brw, "EXT_texture_swizzle or DEPTH_TEXTURE_MODE",
                          old_key->swizzles[i], key->swizzles[i]);
+      found |= key_debug(brw, "texturing needs W-tiling translation",
+                         old_key->num_w_tiled_samples[i],
+                         key->num_w_tiled_samples[i]);
+      found |= key_debug(brw, "W-tiled texture base level changed",
+                         old_key->w_tiled_base_level[i],
+                         key->w_tiled_base_level[i]);
    }
    found |= key_debug(brw, "GL_CLAMP enabled on any texture unit's 1st coordinate",
                       old_key->gl_clamp_mask[0], key->gl_clamp_mask[0]);
@@ -325,6 +331,8 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
 
    for (int s = 0; s < sampler_count; s++) {
       key->swizzles[s] = SWIZZLE_NOOP;
+      key->num_w_tiled_samples[s] = 0;
+      key->w_tiled_base_level[s] = 0;
 
       if (!(prog->SamplersUsed & (1 << s)))
 	 continue;
@@ -383,6 +391,12 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
              intel_tex->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
             key->compressed_multisample_layout_mask |= 1 << s;
          }
+
+         if (brw->gen < 8 && t->StencilSampling) {
+            key->num_w_tiled_samples[s] = intel_tex->mt->num_samples ?
+                                          intel_tex->mt->num_samples : 1;
+            key->w_tiled_base_level[s] = t->BaseLevel;
+         }
       }
    }
 }
-- 
1.8.3.1