[Mesa-dev] [PATCH 1/2] i965: House MOCS settings in brw_context/brw_device_info
ville.syrjala at linux.intel.com
ville.syrjala at linux.intel.com
Wed Jun 17 03:06:45 PDT 2015
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
The layout of the MOCS bits has kept changing for each new
platform. Instead of adding platform checks all over the
place just store the MOCS settings in the device info
and context.
Currently MOCS is only ever set up in two ways: either
let the PTE choose the LLC/eLLC caching mode, or override
it to WB. L3 caching is enabled in both cases. That means
at most two different MOCS settings are required per
platform: "PTE" and "WB".
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_context.c | 3 +++
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
src/mesa/drivers/dri/i965/brw_device_info.c | 12 ++++++++++--
src/mesa/drivers/dri/i965/brw_device_info.h | 3 +++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_misc_state.c | 6 ++----
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 8 +++-----
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 +++---
src/mesa/drivers/dri/i965/gen7_misc_state.c | 7 +++----
src/mesa/drivers/dri/i965/gen7_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +++----
src/mesa/drivers/dri/i965/gen8_depth_state.c | 8 +++-----
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 8 +++-----
src/mesa/drivers/dri/i965/gen8_misc_state.c | 13 ++++++-------
src/mesa/drivers/dri/i965/gen8_sol_state.c | 3 +--
src/mesa/drivers/dri/i965/gen8_surface_state.c | 10 +++-------
17 files changed, 52 insertions(+), 50 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index f39b350..144142e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -756,6 +756,9 @@ brwCreateContext(gl_api api,
brw->needs_unlit_centroid_workaround =
devinfo->needs_unlit_centroid_workaround;
+ brw->mocs_pte = devinfo->mocs_pte;
+ brw->mocs_wb = devinfo->mocs_wb;
+
brw->must_use_separate_stencil = screen->hw_must_use_separate_stencil;
brw->has_swizzling = screen->hw_has_swizzling;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 58119ee..b3d9bf9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1148,6 +1148,8 @@ struct brw_context
*/
bool needs_unlit_centroid_workaround;
+ uint8_t mocs_pte, mocs_wb;
+
GLuint NewGLState;
struct {
struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index bfcc442..3cf778b 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -29,6 +29,8 @@
* Keith Whitwell <keithw at vmware.com>
*/
+#include <util/macros.h>
+
#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
/* Using the GNU statement expression extension */
#define SET_FIELD(value, field) \
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index 97243a4..edcfbd4 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -23,6 +23,7 @@
#include <stdio.h>
#include <stdlib.h>
+#include "brw_defines.h"
#include "brw_device_info.h"
static const struct brw_device_info brw_device_info_i965 = {
@@ -107,7 +108,9 @@ static const struct brw_device_info brw_device_info_snb_gt2 = {
.must_use_separate_stencil = true, \
.has_llc = true, \
.has_pln = true, \
- .has_surface_tile_offset = true
+ .has_surface_tile_offset = true, \
+ .mocs_pte = GEN7_MOCS_L3, \
+ .mocs_wb = GEN7_MOCS_L3
static const struct brw_device_info brw_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
@@ -237,7 +240,9 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = {
.max_hs_threads = 504, \
.max_ds_threads = 504, \
.max_gs_threads = 504, \
- .max_wm_threads = 384
+ .max_wm_threads = 384, \
+ .mocs_pte = BDW_MOCS_PTE, \
+ .mocs_wb = BDW_MOCS_WB
static const struct brw_device_info brw_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
@@ -298,6 +303,7 @@ static const struct brw_device_info brw_device_info_chv = {
};
/* Thread counts and URB limits are placeholders, and may not be accurate. */
+/* FINISHME: Use PTE MOCS on Skylake. */
#define GEN9_FEATURES \
.gen = 9, \
.has_hiz_and_separate_stencil = true, \
@@ -307,6 +313,8 @@ static const struct brw_device_info brw_device_info_chv = {
.max_vs_threads = 280, \
.max_gs_threads = 256, \
.max_wm_threads = 408, \
+ .mocs_pte = SKL_MOCS_WT, \
+ .mocs_wb = SKL_MOCS_WB, \
.urb = { \
.size = 128, \
.min_vs_entries = 64, \
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h b/src/mesa/drivers/dri/i965/brw_device_info.h
index 65c024c..de9d90d 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.h
+++ b/src/mesa/drivers/dri/i965/brw_device_info.h
@@ -24,6 +24,7 @@
#pragma once
#include <stdbool.h>
+#include <stdint.h>
struct brw_device_info
{
@@ -82,6 +83,8 @@ struct brw_device_info
unsigned max_gs_entries;
} urb;
/** @} */
+
+ uint8_t mocs_pte, mocs_wb;
};
const struct brw_device_info *brw_get_device_info(int devid, int revision);
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 320e40e..81acead 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -630,7 +630,7 @@ emit_vertex_buffer_state(struct brw_context *brw,
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
if (brw->gen == 7)
- dw0 |= GEN7_MOCS_L3 << 16;
+ dw0 |= brw->mocs_pte << 16;
WARN_ONCE(stride >= (brw->gen >= 5 ? 2048 : 2047),
"VBO stride %d too large, bad rendering may occur\n",
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 67a693b..a58a135 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -939,12 +939,10 @@ static void upload_state_base_address( struct brw_context *brw )
*/
if (brw->gen >= 6) {
- uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
-
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
- OUT_BATCH(mocs << 8 | /* General State Memory Object Control State */
- mocs << 4 | /* Stateless Data Port Access Memory Object Control State */
+ OUT_BATCH(brw->mocs_pte << 8 | /* General State Memory Object Control State */
+ brw->mocs_pte << 4 | /* Stateless Data Port Access Memory Object Control State */
1); /* General State Base Address Modify Enable */
/* Surface state base address:
* BINDING_TABLE_STATE
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index b6a3d78..fea02d8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -61,12 +61,10 @@ void
gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
{
- uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
-
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
- OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
- mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
+ OUT_BATCH(brw->mocs_pte << 8 | /* GeneralStateMemoryObjectControlState */
+ brw->mocs_pte << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
1); /* GeneralStateBaseAddressModifyEnable */
/* SurfaceStateBaseAddress */
@@ -110,7 +108,7 @@ gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
if (brw->gen == 7)
- dw0 |= GEN7_MOCS_L3 << 16;
+ dw0 |= brw->mocs_pte << 16;
BEGIN_BATCH(batch_length);
OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 2bdc82b..8e10bed 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -145,7 +145,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
*/
struct intel_mipmap_tree *mt = surface->mt;
uint32_t tile_x, tile_y;
- const uint8_t mocs = GEN7_MOCS_L3;
+ const uint8_t mocs = brw->mocs_pte;
uint32_t tiling = surface->map_stencil_as_y_tiled
? I915_TILING_Y : mt->tiling;
@@ -558,7 +558,7 @@ static void
gen7_blorp_emit_constant_ps(struct brw_context *brw,
uint32_t wm_push_const_offset)
{
- const uint8_t mocs = GEN7_MOCS_L3;
+ const uint8_t mocs = brw->mocs_pte;
/* Make sure the push constants fill an exact integer number of
* registers.
@@ -599,7 +599,7 @@ static void
gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
const brw_blorp_params *params)
{
- const uint8_t mocs = GEN7_MOCS_L3;
+ const uint8_t mocs = brw->mocs_pte;
uint32_t surfwidth, surfheight;
uint32_t surftype;
unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index f4f6652..21c0084 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -40,7 +40,6 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t tile_x, uint32_t tile_y)
{
struct gl_context *ctx = &brw->ctx;
- const uint8_t mocs = GEN7_MOCS_L3;
struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t surftype;
unsigned int depth = 1;
@@ -129,7 +128,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw4 */
OUT_BATCH(((depth - 1) << 21) |
(min_array_element << 10) |
- mocs);
+ brw->mocs_pte);
/* 3DSTATE_DEPTH_BUFFER dw5 */
OUT_BATCH(0);
@@ -149,7 +148,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
- OUT_BATCH((mocs << 25) |
+ OUT_BATCH((brw->mocs_pte << 25) |
(hiz_buf->pitch - 1));
OUT_RELOC(hiz_buf->bo,
I915_GEM_DOMAIN_RENDER,
@@ -180,7 +179,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
* same text, and experiments indicate that this is necessary.
*/
OUT_BATCH(enabled |
- mocs << 25 |
+ brw->mocs_pte << 25 |
(2 * stencil_mt->pitch - 1));
OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 278b3ec..4ccfb24 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -35,7 +35,7 @@ gen7_upload_constant_state(struct brw_context *brw,
const struct brw_stage_state *stage_state,
bool active, unsigned opcode)
{
- uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
+ uint8_t mocs = brw->gen < 8 ? brw->mocs_pte : 0;
/* Disable if the shader stage is inactive or there are no push constants. */
active = active && stage_state->push_const_size != 0;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 15ab2b0..4e6fd9a 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -244,7 +244,7 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
surf[3] |= (pitch - 1);
- surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
+ surf[5] = SET_FIELD(brw->mocs_pte, GEN7_SURFACE_MOCS);
if (brw->is_haswell) {
surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
@@ -314,7 +314,7 @@ gen7_emit_texture_surface_state(struct brw_context *brw,
SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
- surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+ surf[5] = (SET_FIELD(brw->mocs_pte, GEN7_SURFACE_MOCS) |
SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
/* mip count */
(max_level - min_level - 1));
@@ -463,7 +463,6 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
uint32_t surftype;
bool is_array = false;
int depth = MAX2(irb->layer_count, 1);
- const uint8_t mocs = GEN7_MOCS_L3;
uint32_t offset;
int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
@@ -523,7 +522,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
assert(brw->has_surface_tile_offset);
- surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
+ surf[5] = SET_FIELD(brw->mocs_pte, GEN7_SURFACE_MOCS) |
(irb->mt_level - irb->mt->first_level);
surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 12ac97a..9978eb7 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -49,8 +49,6 @@ emit_depth_packets(struct brw_context *brw,
uint32_t lod,
uint32_t min_array_element)
{
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
-
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
assert(brw->hw_ctx);
@@ -76,7 +74,7 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(0);
}
OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
- OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
+ OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | brw->mocs_wb);
OUT_BATCH(0);
OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0));
ADVANCE_BATCH();
@@ -92,7 +90,7 @@ emit_depth_packets(struct brw_context *brw,
} else {
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
- OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
+ OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | brw->mocs_wb << 25);
OUT_RELOC64(depth_mt->hiz_buf->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
@@ -124,7 +122,7 @@ emit_depth_packets(struct brw_context *brw,
* page (which would imply that it does). Experiments with the hardware
* indicate that it does.
*/
- OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
+ OUT_BATCH(HSW_STENCIL_ENABLED | brw->mocs_wb << 22 |
(2 * stencil_mt->pitch - 1));
OUT_RELOC64(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
index 1af90ec..1325785 100644
--- a/src/mesa/drivers/dri/i965/gen8_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/gen8_draw_upload.c
@@ -39,7 +39,6 @@ static void
gen8_emit_vertices(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
brw_prepare_vertices(brw);
brw_prepare_shader_draw_parameters(brw);
@@ -120,7 +119,7 @@ gen8_emit_vertices(struct brw_context *brw)
dw0 |= i << GEN6_VB0_INDEX_SHIFT;
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
dw0 |= buffer->stride << BRW_VB0_PITCH_SHIFT;
- dw0 |= mocs_wb << 16;
+ dw0 |= brw->mocs_wb << 16;
OUT_BATCH(dw0);
OUT_RELOC64(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
@@ -130,7 +129,7 @@ gen8_emit_vertices(struct brw_context *brw)
if (brw->vs.prog_data->uses_vertexid) {
OUT_BATCH(brw->vb.nr_buffers << GEN6_VB0_INDEX_SHIFT |
GEN7_VB0_ADDRESS_MODIFYENABLE |
- mocs_wb << 16);
+ brw->mocs_wb << 16);
OUT_RELOC64(brw->draw.draw_params_bo, I915_GEM_DOMAIN_VERTEX, 0,
brw->draw.draw_params_offset);
OUT_BATCH(brw->draw.draw_params_bo->size);
@@ -244,14 +243,13 @@ static void
gen8_emit_index_buffer(struct brw_context *brw)
{
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
if (index_buffer == NULL)
return;
BEGIN_BATCH(5);
OUT_BATCH(CMD_INDEX_BUFFER << 16 | (5 - 2));
- OUT_BATCH(brw_get_index_type(index_buffer->type) | mocs_wb);
+ OUT_BATCH(brw_get_index_type(index_buffer->type) | brw->mocs_wb);
OUT_RELOC64(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_BATCH(brw->ib.bo->size);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index b20038e..37b12e7 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -31,28 +31,27 @@
*/
void gen8_upload_state_base_address(struct brw_context *brw)
{
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = brw->gen >= 9 ? 19 : 16;
BEGIN_BATCH(pkt_len);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
/* General state base address: stateless DP read/write requests */
- OUT_BATCH(mocs_wb << 4 | 1);
+ OUT_BATCH(brw->mocs_wb << 4 | 1);
OUT_BATCH(0);
- OUT_BATCH(mocs_wb << 16);
+ OUT_BATCH(brw->mocs_wb << 16);
/* Surface state base address: */
OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
+ brw->mocs_wb << 4 | 1);
/* Dynamic state base address: */
OUT_RELOC64(brw->batch.bo,
I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ brw->mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
- OUT_BATCH(mocs_wb << 4 | 1);
+ OUT_BATCH(brw->mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ brw->mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
diff --git a/src/mesa/drivers/dri/i965/gen8_sol_state.c b/src/mesa/drivers/dri/i965/gen8_sol_state.c
index 58ead68..4280b14 100644
--- a/src/mesa/drivers/dri/i965/gen8_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sol_state.c
@@ -44,7 +44,6 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
ctx->TransformFeedback.CurrentObject;
struct brw_transform_feedback_object *brw_obj =
(struct brw_transform_feedback_object *) xfb_obj;
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
/* Set up the up to 4 output buffers. These are the ranges defined in the
* gl_transform_feedback_object.
@@ -81,7 +80,7 @@ gen8_upload_3dstate_so_buffers(struct brw_context *brw)
OUT_BATCH(GEN8_SO_BUFFER_ENABLE | (i << SO_BUFFER_INDEX_SHIFT) |
GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE |
GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE |
- (mocs_wb << 22));
+ (brw->mocs_wb << 22));
OUT_RELOC64(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
OUT_BATCH(xfb_obj->Size[i] / 4 - 1);
OUT_RELOC64(brw_obj->offset_bo,
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index b2d1a57..156ba86 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -152,13 +152,12 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
unsigned pitch,
bool rw)
{
- const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
uint32_t *surf = allocate_surface_state(brw, out_offset, -1);
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
- surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
+ surf[1] = SET_FIELD(brw->mocs_wb, GEN8_SURFACE_MOCS);
surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
@@ -196,7 +195,6 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
const unsigned depth = max_layer - min_layer;
struct intel_mipmap_tree *aux_mt = NULL;
uint32_t aux_mode = 0;
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
unsigned tiling_mode, pitch;
const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
@@ -241,7 +239,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP)
surf[0] |= GEN8_SURFACE_IS_ARRAY;
- surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
+ surf[1] = SET_FIELD(brw->mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
@@ -401,8 +399,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
GLenum gl_target =
rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
- /* FINISHME: Use PTE MOCS on Skylake. */
- uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
intel_miptree_used_for_rendering(mt);
@@ -465,7 +461,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
horizontal_alignment(brw, mt, surf_type) |
surface_tiling_mode(tiling);
- surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
+ surf[1] = SET_FIELD(brw->mocs_pte, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
--
2.3.6
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