[Mesa-dev] [PATCH 2/2] i965: Actually enable L3 caching for everything on CHV

ville.syrjala at linux.intel.com ville.syrjala at linux.intel.com
Wed Jun 17 03:06:46 PDT 2015

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Looks like CHV MOCS behaves a bit differently than BDW MOCS. On BDW the
target cache bits can be used to enable L3 caching regardless if how the
other bits are set up to select the UC/WT/WB caching mode for LLC/eLLC.
On CHV however it appears that the other bits control the caching mode
for the specified target cache, which is obviously just L3. So, to
actually enable L3 caching we need to specify L3+WB instead of L3+UC
in the MOCS.

Also note that there is no CPU cache snoop control in MOCS on CHV
like there was on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
 src/mesa/drivers/dri/i965/brw_defines.h     | 6 ++++++
 src/mesa/drivers/dri/i965/brw_device_info.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 3cf778b..2ec7f39 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2493,6 +2493,12 @@ enum brw_wm_barycentric_interp_mode {
 #define BDW_MOCS_WT  0x58
 #define BDW_MOCS_PTE 0x18
+/* Cherryview: always use L3 caching. Apparently we have to
+ * say L3+WB instead of L3+UC to actually get L3 caching.
+ * CPU cache snooping is specifid in the PTE only.
+ */
+#define CHV_MOCS_L3	0x78
 /* Skylake: MOCS is now an index into an array of 64 different configurable
  * cache settings.  We still use only either write-back or write-through; and
  * rely on the documented default values.
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index edcfbd4..4e10c2c 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -292,6 +292,8 @@ static const struct brw_device_info brw_device_info_chv = {
    .max_gs_threads = 80,
    .max_wm_threads = 128,
    .max_cs_threads = 28,
+   .mocs_pte = CHV_MOCS_L3,
+   .mocs_wb = CHV_MOCS_L3,
    .urb = {
       .size = 192,
       .min_vs_entries = 34,

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