[Mesa-dev] [PATCH 3/4] radeonsi: allow tessellation on CU1 and ES on CU0

[Nicolai Hähnle]

On 19.01.2016 20:20, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> We don't use on-chip GS, so it's not required to reserve CU1 for ES.

Why is a deadlock not possible with an off-chip GS ring?

Nicolai

> ---
>   src/gallium/drivers/radeonsi/si_state.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 4b674ed..f005461 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3738,9 +3738,9 @@ static void si_init_config(struct si_context *sctx)
>   	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
>
>   	if (sctx->b.chip_class >= CIK) {
> -		si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
> +		si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
>   		si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
> -		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
> +		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
>   		si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
>