[Mesa-dev] [PATCH 3/4] radeonsi: allow tessellation on CU1 and ES on CU0

[Marek Olšák]

On Wed, Jan 20, 2016 at 6:30 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> On 19.01.2016 20:20, Marek Olšák wrote:
>>
>> From: Marek Olšák <marek.olsak at amd.com>
>>
>> We don't use on-chip GS, so it's not required to reserve CU1 for ES.
>
>
> Why is a deadlock not possible with an off-chip GS ring?

It's about LDS.

On-chip GS uses LDS instead of the rings, which can cause a PS
deadlock just like LS.

We could allow all shaders to run on all CUs if the kernel programmed
SPI_RESOURCE_RESERVE*_CU0 and *_CU1 slightly differently. Those
registers allow reserving a half of LDS for certain stages. For
example, reserving it for PS would mean that PS could use all of CU0
LDS, but LS could only use a half. This is best for chips with only a
few CUs.

Marek