[Mesa-dev] [PATCH 17/18] i965/blorp/gen7+: Stop trashing push constant allocation
Topi Pohjolainen
topi.pohjolainen at intel.com
Thu Jun 23 19:17:13 UTC 2016
Packet 3DSTATE_CONSTANT_PS is still emitted explicitly as ps stage
itself is enabled and hardware may try to prefetch constants from
the buffer. From the BSpec: 3D Pipeline - Windower -
3DSTATE_PUSH_CONSTANT_ALLOC_PS
"Specifies the size of the PS constant buffer. This value will
determine the amount of data the command stream can pre-fetch
before the buffer is full."
This is not possible on gen6. From the BSpec about 3DSTATE_CONSTANT_PS:
"This packet must be followed by WM_STATE."
Binding table emissions for stages other than PS can be now dropped,
they were only needed for the 3DSTATE_CONSTANT_XS to be effective:
>From the BSpec:
"The 3DSTATE_CONSTANT_* command is not committed to the shader unit
until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_*
command is parsed."
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/gen7_blorp.c | 51 +---------------------------------
src/mesa/drivers/dri/i965/gen8_blorp.c | 44 -----------------------------
2 files changed, 1 insertion(+), 94 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index c40192a..7201549 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -69,8 +69,6 @@ void
gen7_blorp_emit_urb_config(struct brw_context *brw,
const struct brw_blorp_params *params)
{
- const unsigned urb_size =
- (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
const unsigned vs_entry_size = gen7_blorp_get_vs_entry_size(params);
if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
@@ -79,13 +77,6 @@ gen7_blorp_emit_urb_config(struct brw_context *brw,
brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
- gen7_emit_push_constant_state(brw,
- urb_size / 2 /* vs_size */,
- 0 /* hs_size */,
- 0 /* ds_size */,
- 0 /* gs_size */,
- urb_size / 2 /* fs_size */);
-
gen7_upload_urb(brw, vs_entry_size, false, false);
}
@@ -245,16 +236,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
static void
gen7_blorp_emit_vs_disable(struct brw_context *brw)
{
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(0);
@@ -274,16 +255,6 @@ static void
gen7_blorp_emit_hs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
- BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -318,16 +289,6 @@ gen7_blorp_emit_te_disable(struct brw_context *brw)
static void
gen7_blorp_emit_ds_disable(struct brw_context *brw)
{
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
OUT_BATCH(0);
@@ -345,16 +306,6 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw)
static void
gen7_blorp_emit_gs_disable(struct brw_context *brw)
{
- BEGIN_BATCH(7);
- OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
/**
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
* Geometry > Geometry Shader > State:
@@ -846,7 +797,7 @@ gen7_blorp_exec(struct brw_context *brw,
if (params->wm_prog_data)
gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
- gen7_blorp_emit_constant_ps_disable(brw);
+ gen7_blorp_emit_constant_ps_disable(brw);
if (params->src.mt) {
const uint32_t sampler_offset =
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c
index 5d10a91..7ca24a8 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -156,36 +156,6 @@ gen8_blorp_emit_blend_state(struct brw_context *brw,
return blend_state_offset;
}
-static void
-gen8_blorp_emit_disable_constant_state(struct brw_context *brw,
- unsigned opcode)
-{
- BEGIN_BATCH(11);
- OUT_BATCH(opcode << 16 | (11 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-}
-
-static void
-gen8_blorp_emit_disable_binding_table(struct brw_context *brw,
- unsigned opcode)
-{
-
- BEGIN_BATCH(2);
- OUT_BATCH(opcode << 16 | (2 - 2));
- OUT_BATCH(0);
- ADVANCE_BATCH();
-}
-
/* 3DSTATE_VS
*
* Disable vertex shader.
@@ -687,23 +657,9 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
const uint32_t cc_state_offset = gen6_blorp_emit_cc_state(brw);
gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
- gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
- gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
- gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
- gen8_blorp_emit_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
-
gen8_blorp_emit_disable_constant_ps(brw);
wm_bind_bo_offset = gen8_blorp_emit_surface_states(brw, params);
- gen8_blorp_emit_disable_binding_table(brw,
- _3DSTATE_BINDING_TABLE_POINTERS_VS);
- gen8_blorp_emit_disable_binding_table(brw,
- _3DSTATE_BINDING_TABLE_POINTERS_HS);
- gen8_blorp_emit_disable_binding_table(brw,
- _3DSTATE_BINDING_TABLE_POINTERS_DS);
- gen8_blorp_emit_disable_binding_table(brw,
- _3DSTATE_BINDING_TABLE_POINTERS_GS);
-
gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
if (params->src.mt) {
--
2.5.5
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