[Mesa-dev] [PATCH v2 31/34] i965/state: Account for the element size in emit_buffer_surface_state
Pohjolainen, Topi
topi.pohjolainen at intel.com
Tue Jun 28 06:22:49 UTC 2016
On Thu, Jun 23, 2016 at 02:00:30PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++++++-----
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 9 +++++----
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 +++++----
> 3 files changed, 16 insertions(+), 13 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 944d64d..29b8976 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -496,6 +496,7 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
> unsigned pitch,
> bool rw)
> {
> + unsigned elements = buffer_size / pitch;
Could be const as well as in the two other occurences further down.
> uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> 6 * 4, 32, out_offset);
> memset(surf, 0, 6 * 4);
> @@ -504,9 +505,9 @@ gen4_emit_buffer_surface_state(struct brw_context *brw,
> surface_format << BRW_SURFACE_FORMAT_SHIFT |
> (brw->gen >= 6 ? BRW_SURFACE_RC_READ_WRITE : 0);
> surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
> - surf[2] = ((buffer_size - 1) & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
> - (((buffer_size - 1) >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
> - surf[3] = (((buffer_size - 1) >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
> + surf[2] = ((elements - 1) & 0x7f) << BRW_SURFACE_WIDTH_SHIFT |
> + (((elements - 1) >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT;
> + surf[3] = (((elements - 1) >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT |
> (pitch - 1) << BRW_SURFACE_PITCH_SHIFT;
>
> /* Emit relocation to surface contents. The 965 PRM, Volume 4, section
> @@ -549,7 +550,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
> brw->vtbl.emit_buffer_surface_state(brw, surf_offset, bo,
> tObj->BufferOffset,
> brw_format,
> - size / texel_size,
> + size,
> texel_size,
> false /* rw */);
> }
> @@ -1480,7 +1481,7 @@ update_image_surface(struct brw_context *brw,
>
> brw->vtbl.emit_buffer_surface_state(
> brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
> - format, intel_obj->Base.Size / texel_size, texel_size,
> + format, intel_obj->Base.Size, texel_size,
> access != GL_READ_ONLY);
>
> update_buffer_image_param(brw, u, surface_idx, param);
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> index bb94f2d..65a1cb0 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
> @@ -135,6 +135,7 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
> unsigned pitch,
> bool rw)
> {
> + unsigned elements = buffer_size / pitch;
> uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> 8 * 4, 32, out_offset);
> memset(surf, 0, 8 * 4);
> @@ -143,12 +144,12 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
> surface_format << BRW_SURFACE_FORMAT_SHIFT |
> BRW_SURFACE_RC_READ_WRITE;
> surf[1] = (bo ? bo->offset64 : 0) + buffer_offset; /* reloc */
> - surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
> - SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
> + surf[2] = SET_FIELD((elements - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
> + SET_FIELD(((elements - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
> if (surface_format == BRW_SURFACEFORMAT_RAW)
> - surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
> + surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
> else
> - surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
> + surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
> surf[3] |= (pitch - 1);
>
> surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index 00e4c48..9ac8a48 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -63,6 +63,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
> unsigned pitch,
> bool rw)
> {
> + unsigned elements = buffer_size / pitch;
> const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
> uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1);
>
> @@ -71,12 +72,12 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
> BRW_SURFACE_RC_READ_WRITE;
> surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
>
> - surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
> - SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
> + surf[2] = SET_FIELD((elements - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
> + SET_FIELD(((elements - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
> if (surface_format == BRW_SURFACEFORMAT_RAW)
> - surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
> + surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3ff, BRW_SURFACE_DEPTH);
> else
> - surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
> + surf[3] = SET_FIELD(((elements - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH);
> surf[3] |= (pitch - 1);
> surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) |
> SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
> --
> 2.5.0.400.gff86faf
>
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