[Mesa-dev] [PATCH 32/36] i965/blorp: Simplify depth buffer state setup a bit
Jason Ekstrand
jason at jlekstrand.net
Thu Jun 30 00:37:51 UTC 2016
The data comes in via ISL in a format that's almost directly usable by the
hardware so we can avoid some of the conversion headache.
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 34 ++++++++----------------------
src/mesa/drivers/dri/i965/gen7_blorp.c | 38 +++++++---------------------------
2 files changed, 17 insertions(+), 55 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c
index f3ed936..a0f36b2 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -684,11 +684,8 @@ static void
gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
const struct brw_blorp_params *params)
{
- uint32_t surfwidth, surfheight;
uint32_t surftype;
- unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
GLenum gl_target = params->depth.mt->target;
- unsigned int lod;
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -699,39 +696,25 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);
break;
}
- const unsigned min_array_element = params->depth.layer;
-
- lod = params->depth.level - params->depth.mt->first_level;
-
- if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
- /* HIZ ops for lod 0 may set the width & height a little
- * larger to allow the fast depth clear to fit the hardware
- * alignment requirements. (8x4)
- */
- surfwidth = params->depth.surf.logical_level0_px.width;
- surfheight = params->depth.surf.logical_level0_px.height;
- } else {
- surfwidth = params->depth.mt->logical_width0;
- surfheight = params->depth.mt->logical_height0;
- }
-
/* 3DSTATE_DEPTH_BUFFER */
{
brw_emit_depth_stall_flushes(brw);
+ unsigned depth = MAX2(params->depth.surf.logical_level0_px.depth,
+ params->depth.surf.logical_level0_px.array_len);
+
BEGIN_BATCH(7);
/* 3DSTATE_DEPTH_BUFFER dw0 */
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
/* 3DSTATE_DEPTH_BUFFER dw1 */
- OUT_BATCH((params->depth.mt->pitch - 1) |
+ OUT_BATCH((params->depth.surf.row_pitch - 1) |
params->depth_format << 18 |
1 << 21 | /* separate stencil enable */
1 << 22 | /* hiz enable */
@@ -746,13 +729,13 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
/* 3DSTATE_DEPTH_BUFFER dw3 */
OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 |
- (surfwidth - 1) << 6 |
- (surfheight - 1) << 19 |
- lod << 2);
+ (params->depth.surf.logical_level0_px.width - 1) << 6 |
+ (params->depth.surf.logical_level0_px.height - 1) << 19 |
+ params->depth.view.base_level << 2);
/* 3DSTATE_DEPTH_BUFFER dw4 */
OUT_BATCH((depth - 1) << 21 |
- min_array_element << 10 |
+ params->depth.view.base_array_layer << 10 |
(depth - 1) << 1);
/* 3DSTATE_DEPTH_BUFFER dw5 */
@@ -769,6 +752,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
uint32_t offset = 0;
if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
+ const unsigned lod = params->depth.view.base_level;
offset = intel_miptree_get_aligned_offset(hiz_mt,
hiz_mt->level[lod].level_x,
hiz_mt->level[lod].level_y,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 5e37a85..3d66eb1 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -551,12 +551,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
const struct brw_blorp_params *params)
{
const uint8_t mocs = GEN7_MOCS_L3;
- uint32_t surfwidth, surfheight;
uint32_t surftype;
- unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
- unsigned int min_array_element;
GLenum gl_target = params->depth.mt->target;
- unsigned int lod;
switch (gl_target) {
case GL_TEXTURE_CUBE_MAP_ARRAY:
@@ -567,40 +563,22 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
* equivalent.
*/
surftype = BRW_SURFACE_2D;
- depth *= 6;
break;
default:
surftype = translate_tex_target(gl_target);
break;
}
- min_array_element = params->depth.layer;
- if (params->depth.mt->num_samples > 1) {
- /* Convert physical layer to logical layer. */
- min_array_element /= params->depth.mt->num_samples;
- }
-
- lod = params->depth.level - params->depth.mt->first_level;
-
- if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
- /* HIZ ops for lod 0 may set the width & height a little
- * larger to allow the fast depth clear to fit the hardware
- * alignment requirements. (8x4)
- */
- surfwidth = params->depth.surf.logical_level0_px.width;
- surfheight = params->depth.surf.logical_level0_px.height;
- } else {
- surfwidth = params->depth.mt->logical_width0;
- surfheight = params->depth.mt->logical_height0;
- }
-
/* 3DSTATE_DEPTH_BUFFER */
{
brw_emit_depth_stall_flushes(brw);
+ unsigned depth = MAX2(params->depth.surf.logical_level0_px.depth,
+ params->depth.surf.logical_level0_px.array_len);
+
BEGIN_BATCH(7);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
- OUT_BATCH((params->depth.mt->pitch - 1) |
+ OUT_BATCH((params->depth.surf.row_pitch - 1) |
params->depth_format << 18 |
1 << 22 | /* hiz enable */
1 << 28 | /* depth write */
@@ -608,11 +586,11 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
OUT_RELOC(params->depth.mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
- OUT_BATCH((surfwidth - 1) << 4 |
- (surfheight - 1) << 18 |
- lod);
+ OUT_BATCH((params->depth.surf.logical_level0_px.width - 1) << 4 |
+ (params->depth.surf.logical_level0_px.height - 1) << 18 |
+ params->depth.view.base_level);
OUT_BATCH(((depth - 1) << 21) |
- (min_array_element << 10) |
+ (params->depth.view.base_array_layer << 10) |
mocs);
OUT_BATCH(0);
OUT_BATCH((depth - 1) << 21);
--
2.5.0.400.gff86faf
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