[Mesa-dev] [PATCH 0/3] i965/vec4: Make offset() work in terms of width and scalar channels

Iago Toral Quiroga itoral at igalia.com
Tue Oct 4 07:52:16 UTC 2016

The semantics of offset() differ between the align16 backend, where it works in
terms of registers, and the scalar backend, where it works in terms of a simd
width and the size of the scalar channels. During review of the fp64 align16
code, Curro suggested that some things could be simpler if made the align16
version of offset() work with the same semantics as its scalar counterpart [1].

This series changes the implementation of offset() accordingly and also adds
a byte_offset() helper, then adapts all calls to offset() to match the new
semantics or, where it is more convenient, use the byte_offset() helper.

AFAIK the dispatch width in align16 is always 8, so I wonder if it makes
sense to have a width parameter in the signature of offset, like we have in the 
scalar backend, instead of fixing the width to 8 internally...

[1] https://lists.freedesktop.org/archives/mesa-dev/2016-August/125057.html

Iago Toral Quiroga (3):
  i965/vec4: add a byte_offset helper
  i965/vec4: use byte_offset() instead of offset()
  i965/vec4: make offset() work in terms of a simd width and scalar

 src/mesa/drivers/dri/i965/brw_ir_vec4.h            | 58 ++++++++++++++++++++--
 src/mesa/drivers/dri/i965/brw_vec4_cse.cpp         | 10 ++--
 .../dri/i965/brw_vec4_dead_code_eliminate.cpp      | 16 ++++--
 .../drivers/dri/i965/brw_vec4_live_variables.cpp   | 13 +++--
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp         |  2 +-
 .../drivers/dri/i965/brw_vec4_surface_builder.cpp  | 14 +++---
 src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp         |  3 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp     |  2 +-
 8 files changed, 91 insertions(+), 27 deletions(-)


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