[Mesa-dev] [PATCH 16/22] i965/vec4: consider subregister offset in live variables

[Samuel Iglesias Gonsálvez]

From: "Juan A. Suarez Romero" <jasuarez at igalia.com>

Take in account the offset value when getting the var from register.

This is required when dealing with an operation that writes half of the
register (like one d2x in IVB/VLV, which uses exec_size == 4).

Note that for live analysis variables we need to stick to per-GRF
analysis. In this case, we use var_from_reg() with GRF precision.
---
 src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp | 12 ++++++++----
 src/mesa/drivers/dri/i965/brw_vec4_live_variables.h   | 10 ++++++----
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
index 73f658c..54ebd09 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
@@ -78,7 +78,8 @@ vec4_live_variables::setup_def_use()
 	    if (inst->src[i].file == VGRF) {
                for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) {
                   for (int c = 0; c < 4; c++) {
-                     const unsigned v = var_from_reg(alloc, inst->src[i], c, j);
+                     const unsigned v =
+                        var_from_reg(alloc, inst->src[i], c, j, false);
                      if (!BITSET_TEST(bd->def, v))
                         BITSET_SET(bd->use, v);
                   }
@@ -101,7 +102,8 @@ vec4_live_variables::setup_def_use()
             for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
                for (int c = 0; c < 4; c++) {
                   if (inst->dst.writemask & (1 << c)) {
-                     const unsigned v = var_from_reg(alloc, inst->dst, c, i);
+                     const unsigned v =
+                        var_from_reg(alloc, inst->dst, c, i, false);
                      if (!BITSET_TEST(bd->use, v))
                         BITSET_SET(bd->def, v);
                   }
@@ -257,7 +259,8 @@ vec4_visitor::calculate_live_intervals()
 	 if (inst->src[i].file == VGRF) {
             for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) {
                for (int c = 0; c < 4; c++) {
-                  const unsigned v = var_from_reg(alloc, inst->src[i], c, j);
+                  const unsigned v =
+                     var_from_reg(alloc, inst->src[i], c, j, false);
                   start[v] = MIN2(start[v], ip);
                   end[v] = ip;
                }
@@ -269,7 +272,8 @@ vec4_visitor::calculate_live_intervals()
          for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
             for (int c = 0; c < 4; c++) {
                if (inst->dst.writemask & (1 << c)) {
-                  const unsigned v = var_from_reg(alloc, inst->dst, c, i);
+                  const unsigned v =
+                     var_from_reg(alloc, inst->dst, c, i, false);
                   start[v] = MIN2(start[v], ip);
                   end[v] = ip;
                }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
index 8807c45..9c505d1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h
@@ -83,13 +83,14 @@ protected:
  */
 inline unsigned
 var_from_reg(const simple_allocator &alloc, const src_reg &reg,
-             unsigned c = 0, unsigned k = 0)
+             unsigned c = 0, unsigned k = 0, bool subreg_precision = true)
 {
    assert(reg.file == VGRF && reg.nr < alloc.count && c < 4);
    const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
    unsigned result =
       8 * (alloc.offsets[reg.nr] + reg.offset / REG_SIZE) +
-      (BRW_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize;
+      (BRW_GET_SWZ(reg.swizzle, c) + k / csize * 4) * csize + k % csize +
+      (subreg_precision ? (reg.offset % REG_SIZE) / type_sz(reg.type) : 0);
    /* Do not exceed the limit for this register */
    assert(result < 8 * (alloc.offsets[reg.nr] + alloc.sizes[reg.nr]));
    return result;
@@ -97,13 +98,14 @@ var_from_reg(const simple_allocator &alloc, const src_reg &reg,
 
 inline unsigned
 var_from_reg(const simple_allocator &alloc, const dst_reg &reg,
-             unsigned c = 0, unsigned k = 0)
+             unsigned c = 0, unsigned k = 0, bool subreg_precision = true)
 {
    assert(reg.file == VGRF && reg.nr < alloc.count && c < 4);
    const unsigned csize = DIV_ROUND_UP(type_sz(reg.type), 4);
    unsigned result =
       8 * (alloc.offsets[reg.nr] + reg.offset / REG_SIZE) +
-      (c + k / csize * 4) * csize + k % csize;
+      (c + k / csize * 4) * csize + k % csize +
+      (subreg_precision ? (reg.offset % REG_SIZE) / type_sz(reg.type) : 0);
    /* Do not exceed the limit for this register */
    assert(result < 8 * (alloc.offsets[reg.nr] + alloc.sizes[reg.nr]));
    return result;
-- 
2.9.3