[Mesa-dev] [PATCH 13/51] i965: Rename render_cache dirty tracking to reduce later churn
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:36 UTC 2017
Simple rename and parameter passing changes now to avoid doing so inside
a much larger patch.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_batch.h | 5 +++++
src/mesa/drivers/dri/i965/brw_context.c | 12 ++++++----
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_draw.c | 6 ++---
src/mesa/drivers/dri/i965/brw_misc_state.c | 8 +++----
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 ++
src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 11 +++------
src/mesa/drivers/dri/i965/intel_fbo.c | 32 +++++++--------------------
src/mesa/drivers/dri/i965/intel_fbo.h | 4 ----
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++-
11 files changed, 38 insertions(+), 49 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_batch.h b/src/mesa/drivers/dri/i965/brw_batch.h
index 860f1950f4..0f7c97aedf 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.h
+++ b/src/mesa/drivers/dri/i965/brw_batch.h
@@ -33,6 +33,8 @@ extern "C" {
#include <intel_bufmgr.h>
+#include "util/list.h"
+
typedef drm_intel_bo brw_bo;
enum brw_gpu_ring {
@@ -98,6 +100,9 @@ inline static uint32_t brw_bo_flink(brw_bo *bo)
return name;
}
+void brw_batch_clear_dirty(brw_batch *batch);
+void brw_bo_mark_dirty(brw_batch *batch, brw_bo *bo);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index d09127a951..1f5e0c86af 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -263,7 +263,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
const int flags = intel_texture_view_requires_resolve(brw, tex_obj) ?
0 : INTEL_MIPTREE_IGNORE_CCS_E;
intel_miptree_all_slices_resolve_color(brw, tex_obj->mt, flags);
- brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+ if (brw_check_dirty(brw, tex_obj->mt->bo))
+ brw_emit_mi_flush(brw);
if (tex_obj->base.StencilSampling ||
tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
@@ -299,7 +300,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
"off lossless compression");
}
- brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+ if (brw_check_dirty(brw, tex_obj->mt->bo))
+ brw_emit_mi_flush(brw);
}
}
}
@@ -319,7 +321,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
intel_miptree_resolve_color(
brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count,
INTEL_MIPTREE_IGNORE_CCS_E))
- brw_render_cache_set_check_flush(brw, irb->mt->bo);
+ if (brw_check_dirty(brw, irb->mt->bo))
+ brw_emit_mi_flush(brw);
}
}
@@ -350,7 +353,8 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
*/
assert(!intel_miptree_is_lossless_compressed(brw, mt));
intel_miptree_all_slices_resolve_color(brw, mt, 0);
- brw_render_cache_set_check_flush(brw, mt->bo);
+ if (brw_check_dirty(brw, mt->bo))
+ brw_emit_mi_flush(brw);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 8051db12be..88d9a52c0a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1710,6 +1710,8 @@ void brw_emit_depth_stall_flushes(struct brw_context *brw);
void gen7_emit_vs_workaround_flush(struct brw_context *brw);
void gen7_emit_cs_stall_flush(struct brw_context *brw);
+bool brw_check_dirty(struct brw_context *ctx, brw_bo *bo);
+
/* brw_queryformat.c */
void brw_query_internal_format(struct gl_context *ctx, GLenum target,
GLenum internalFormat, GLenum pname,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 55ff0ba7a0..17ef0f202e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -373,12 +373,12 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
back_irb->need_downsample = true;
if (depth_irb && brw_depth_writes_enabled(brw)) {
intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
- brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, depth_irb->mt->bo);
}
if (ctx->Extensions.ARB_stencil_texturing &&
stencil_irb && ctx->Stencil._WriteEnabled) {
- brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, stencil_irb->mt->bo);
}
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
@@ -388,7 +388,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context *brw)
if (!irb)
continue;
- brw_render_cache_set_add_bo(brw, irb->mt->bo);
+ brw_bo_mark_dirty(&brw->batch, irb->mt->bo);
intel_miptree_used_for_rendering(
brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count);
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 0b2984465f..3b23440fc8 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -551,10 +551,10 @@ brw_emit_depthbuffer(struct brw_context *brw)
height = stencil_irb->Base.Base.Height;
}
- if (depth_mt)
- brw_render_cache_set_check_flush(brw, depth_mt->bo);
- if (stencil_mt)
- brw_render_cache_set_check_flush(brw, stencil_mt->bo);
+ if (depth_mt && brw_check_dirty(brw, depth_mt->bo))
+ brw_emit_mi_flush(brw);
+ if (stencil_mt && brw_check_dirty(brw, stencil_mt->bo))
+ brw_emit_mi_flush(brw);
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 658b8e8dd9..79fddf7555 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -358,6 +358,8 @@ brw_emit_mi_flush(struct brw_context *brw)
}
brw_emit_pipe_control_flush(brw, flags);
}
+
+ brw_batch_clear_dirty(&brw->batch);
}
int
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index d3d11705f0..ea79ab7346 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -511,7 +511,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
ADVANCE_BATCH();
/* Mark this buffer as needing a TC flush, as we've rendered to it. */
- brw_render_cache_set_add_bo(brw, mt->bo);
+ brw_bo_mark_dirty(&brw->batch, mt->bo);
/* We've clobbered all of the depth packets, and the drawing rectangle,
* so we need to ensure those packets are re-emitted before the next
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 8cf549706e..2bf9583172 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -60,6 +60,8 @@ intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
brw_bo_put(batch->last_bo);
batch->last_bo = batch->bo;
+ brw_batch_clear_dirty(batch);
+
batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
if (has_llc) {
drm_intel_bo_map(batch->bo, true);
@@ -78,13 +80,6 @@ intel_batchbuffer_reset(struct brw_batch *batch, dri_bufmgr *bufmgr,
batch->ring = UNKNOWN_RING;
}
-static void
-intel_batchbuffer_reset_and_clear_render_cache(struct brw_context *brw)
-{
- intel_batchbuffer_reset(&brw->batch, brw->bufmgr, brw->has_llc);
- brw_render_cache_set_clear(brw);
-}
-
void
intel_batchbuffer_save_state(struct brw_context *brw)
{
@@ -191,7 +186,7 @@ brw_new_batch(struct brw_context *brw)
{
/* Create a new batchbuffer and reset the associated state: */
drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0);
- intel_batchbuffer_reset_and_clear_render_cache(brw);
+ intel_batchbuffer_reset(&brw->batch, brw->bufmgr, brw->has_llc);
/* If the kernel supports hardware contexts, then most hardware state is
* preserved between batches; we only need to re-emit state that is required
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 627a81111f..f892be4009 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -1047,19 +1047,19 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
}
void
-brw_render_cache_set_clear(struct brw_context *brw)
+brw_batch_clear_dirty(brw_batch *batch)
{
struct set_entry *entry;
- set_foreach(brw->batch.render_cache, entry) {
- _mesa_set_remove(brw->batch.render_cache, entry);
+ set_foreach(batch->render_cache, entry) {
+ _mesa_set_remove(batch->render_cache, entry);
}
}
void
-brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo)
+brw_bo_mark_dirty(brw_batch *batch, brw_bo *bo)
{
- _mesa_set_add(brw->batch.render_cache, bo);
+ _mesa_set_add(batch->render_cache, bo);
}
/**
@@ -1074,26 +1074,10 @@ brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo)
* necessary is flushed before another use of that BO, but for reuse from
* different caches within a batchbuffer, it's all our responsibility.
*/
-void
-brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo)
+bool
+brw_check_dirty(struct brw_context *brw, brw_bo *bo)
{
- if (!_mesa_set_search(brw->batch.render_cache, bo))
- return;
-
- if (brw->gen >= 6) {
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
-
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
- PIPE_CONTROL_CONST_CACHE_INVALIDATE);
- } else {
- brw_emit_mi_flush(brw);
- }
-
- brw_render_cache_set_clear(brw);
+ return _mesa_set_search(brw->batch.render_cache, bo);
}
/**
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h b/src/mesa/drivers/dri/i965/intel_fbo.h
index 094eb61915..b6068607a2 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -235,10 +235,6 @@ void
intel_renderbuffer_upsample(struct brw_context *brw,
struct intel_renderbuffer *irb);
-void brw_render_cache_set_clear(struct brw_context *brw);
-void brw_render_cache_set_add_bo(struct brw_context *brw, brw_bo *bo);
-void brw_render_cache_set_check_flush(struct brw_context *brw, brw_bo *bo);
-
unsigned
intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 88baed2bdb..95d7a82f20 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2488,7 +2488,8 @@ intel_update_r8stencil(struct brw_context *brw,
}
}
- brw_render_cache_set_check_flush(brw, dst->bo);
+ if (brw_check_dirty(brw, dst->bo))
+ brw_emit_mi_flush(brw);
src->r8stencil_needs_update = false;
}
--
2.11.0
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