[Mesa-dev] [PATCH 39/51] i965: Convert brw_emit_mi_flush() to use batch begin/end
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:24:02 UTC 2017
We have many flushes outside of the batch buffer critical sections that
need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush()
with the begin/end.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_clear.c | 4 +--
src/mesa/drivers/dri/i965/brw_context.c | 6 ++---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_pipe_control.c | 33 +++++++++++++++++-------
src/mesa/drivers/dri/i965/brw_sync.c | 2 +-
src/mesa/drivers/dri/i965/gen6_sol.c | 3 +--
src/mesa/drivers/dri/i965/intel_blit.c | 2 +-
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 4 +--
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex.c | 12 +--------
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
11 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index e419b8e049..ed1c9d12e4 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -180,7 +180,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* must be issued before the rectangle primitive used for the depth
* buffer clear operation.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
if (fb->MaxNumLayers > 0) {
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
@@ -200,7 +200,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
* followed by Depth FLUSH'
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 2fe77517ca..4ee766e94f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -264,7 +264,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
0 : INTEL_MIPTREE_IGNORE_CCS_E;
intel_miptree_all_slices_resolve_color(brw, tex_obj->mt, flags);
if (brw_check_dirty(brw, tex_obj->mt->bo))
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
if (tex_obj->base.StencilSampling ||
tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
@@ -301,7 +301,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
}
if (brw_check_dirty(brw, tex_obj->mt->bo))
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
}
}
@@ -354,7 +354,7 @@ intel_update_state(struct gl_context * ctx, GLuint new_state)
assert(!intel_miptree_is_lossless_compressed(brw, mt));
intel_miptree_all_slices_resolve_color(brw, mt, 0);
if (brw_check_dirty(brw, mt->bo))
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 26645ac812..8e95674543 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1679,6 +1679,8 @@ void brw_emit_depth_stall_flushes(struct brw_context *brw);
void gen7_emit_vs_workaround_flush(struct brw_context *brw);
void gen7_emit_cs_stall_flush(struct brw_context *brw);
+void brw_mi_flush(struct brw_context *brw, enum brw_gpu_ring ring);
+
bool brw_check_dirty(struct brw_context *ctx, brw_bo *bo);
/* brw_queryformat.c */
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 4195eb932c..7743e3404e 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -353,22 +353,35 @@ brw_emit_mi_flush(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
+ } else if (brw->gen >= 6) {
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_CS_STALL);
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_INSTRUCTION_INVALIDATE |
+ PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
+ PIPE_CONTROL_VF_CACHE_INVALIDATE |
+ PIPE_CONTROL_CONST_CACHE_INVALIDATE);
} else {
- int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
- if (brw->gen >= 6) {
- flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
- PIPE_CONTROL_CONST_CACHE_INVALIDATE |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_VF_CACHE_INVALIDATE |
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
- PIPE_CONTROL_CS_STALL;
- }
- brw_emit_pipe_control_flush(brw, flags);
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_NO_WRITE |
+ PIPE_CONTROL_RENDER_TARGET_FLUSH);
+
}
brw_batch_clear_dirty(&brw->batch);
}
+void
+brw_mi_flush(struct brw_context *brw, enum brw_gpu_ring ring)
+{
+ if (brw_batch_begin(&brw->batch, 60, ring) >= 0) {
+ brw_emit_mi_flush(brw);
+ brw_batch_end(&brw->batch);
+ }
+}
+
int
brw_init_pipe_control(struct brw_context *brw,
const struct gen_device_info *devinfo)
diff --git a/src/mesa/drivers/dri/i965/brw_sync.c b/src/mesa/drivers/dri/i965/brw_sync.c
index 9b5ca873be..13868b8c69 100644
--- a/src/mesa/drivers/dri/i965/brw_sync.c
+++ b/src/mesa/drivers/dri/i965/brw_sync.c
@@ -78,7 +78,7 @@ brw_fence_insert(struct brw_context *brw, struct brw_fence *fence)
assert(!fence->batch_bo);
assert(!fence->signalled);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, RENDER_RING);
fence->batch_bo = brw_bo_get(brw->batch.bo);
brw_batch_flush(&brw->batch, PERF_DEBUG(brw, "SyncFence"));
}
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c
index c634086f5d..7a0ac11b2e 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -288,6 +288,5 @@ brw_end_transform_feedback(struct gl_context *ctx,
* least the GS stage of the pipeline, and flush out the render cache. For
* simplicity, just do a full flush.
*/
- struct brw_context *brw = brw_context(ctx);
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw_context(ctx), RENDER_RING);
}
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index 6208cc5e18..1c42321fae 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -645,7 +645,7 @@ intelEmitCopyBlit(struct brw_context *brw,
*
* FIXME: Figure out a way to avoid flushing when not required.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
assert(cpp <= 16);
BR13 = br13_for_cpp(cpp);
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 70d2c7cc36..137297c087 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -559,7 +559,7 @@ brw_unmap_buffer(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
brw_bo_put(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;
@@ -631,7 +631,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 3dcce792ef..e17b6d8876 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -232,7 +232,7 @@ intelReadPixels(struct gl_context * ctx,
* rendered to via a PBO at any point, so it seems better to just
* flush here unconditionally.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
return;
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 8140d1adf7..239358f2cc 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -365,17 +365,7 @@ intel_texture_barrier(struct gl_context *ctx)
{
struct brw_context *brw = brw_context(ctx);
- if (brw->gen >= 6) {
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_CS_STALL);
-
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
- } else {
- brw_emit_mi_flush(brw);
- }
+ brw_mi_flush(brw, RENDER_RING);
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 79427abff8..454766cb9f 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -587,7 +587,7 @@ intel_get_tex_sub_image(struct gl_context *ctx,
* See the related comment in intelReadPixels() for a more detailed
* explanation.
*/
- brw_emit_mi_flush(brw);
+ brw_mi_flush(brw, BLT_RING);
return;
}
--
2.11.0
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