[Mesa-dev] [PATCH 19/51] i965: Simplify parameters to brw_emit_pipe_control_write()
Chris Wilson
chris at chris-wilson.co.uk
Tue Jan 10 21:23:42 UTC 2017
Rather than passing the uint64_t value to write as a pair of high/lo
uint32_t values, place the burden on the callee to split the large value
into the dwords desired by the hardware.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +--
src/mesa/drivers/dri/i965/brw_pipe_control.c | 33 +++++++++++++++++-----------
src/mesa/drivers/dri/i965/brw_queryobj.c | 4 ++--
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 2 +-
5 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c304a8a6da..ff0e9d7c64 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1674,8 +1674,7 @@ void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- brw_bo *bo, uint32_t offset,
- uint32_t imm_lower, uint32_t imm_upper);
+ brw_bo *bo, uint32_t offset, uint64_t imm);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
void brw_emit_depth_stall_flushes(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 79fddf7555..4195eb932c 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -166,6 +166,16 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
}
}
+inline static uint32_t lower_32_bits(uint64_t x)
+{
+ return x;
+}
+
+inline static uint32_t upper_32_bits(uint64_t x)
+{
+ return x >> 32;
+}
+
/**
* Emit a PIPE_CONTROL that writes to a buffer object.
*
@@ -176,8 +186,7 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
*/
void
brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
- brw_bo *bo, uint32_t offset,
- uint32_t imm_lower, uint32_t imm_upper)
+ brw_bo *bo, uint32_t offset, uint64_t imm)
{
if (brw->gen >= 8) {
if (brw->gen == 8)
@@ -188,8 +197,8 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(lower_32_bits(imm));
+ OUT_BATCH(upper_32_bits(imm));
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
@@ -204,16 +213,16 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
gen6_gtt | offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(lower_32_bits(imm));
+ OUT_BATCH(upper_32_bits(imm));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(lower_32_bits(imm));
+ OUT_BATCH(upper_32_bits(imm));
ADVANCE_BATCH();
}
}
@@ -263,8 +272,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,
- brw->workaround_bo, 0,
- 0, 0);
+ brw->workaround_bo, 0, 0);
}
@@ -277,8 +285,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0,
- 0, 0);
+ brw->workaround_bo, 0, 0);
}
@@ -327,7 +334,7 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0, 0);
+ brw->workaround_bo, 0, 0);
}
/* Emit a pipelined flush to either flush render and texture cache for
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 3f2689dbb6..186aa217cc 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -60,7 +60,7 @@ brw_write_timestamp(struct brw_context *brw, brw_bo *query_bo, int idx)
flags |= PIPE_CONTROL_CS_STALL;
brw_emit_pipe_control_write(brw, flags,
- query_bo, idx * sizeof(uint64_t), 0, 0);
+ query_bo, idx * sizeof(uint64_t), 0);
}
/**
@@ -76,7 +76,7 @@ brw_write_depth_count(struct brw_context *brw, brw_bo *query_bo, int idx)
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
- 0, 0);
+ 0);
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 732cba8c92..a2b22c9247 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -71,7 +71,7 @@ set_query_availability(struct brw_context *brw, struct brw_query_object *query,
brw_emit_pipe_control_write(brw, flags,
query->bo, 2 * sizeof(uint64_t),
- available, 0);
+ available);
}
}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 892c97fd85..cfc9e7ab6e 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -498,7 +498,7 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
*/
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0, 0);
+ brw->workaround_bo, 0, 0);
/* Emit 3DSTATE_WM_HZ_OP again to disable the state overrides. */
BEGIN_BATCH(5);
--
2.11.0
More information about the mesa-dev
mailing list