[Mesa-dev] [PATCH 18/51] i965: Refactor setting a register with an immediate constant

[Chris Wilson]

We have a few instances where we set a register to an immediate value
(MI_LOAD_REGISTER_IMM), so let's replace them with a simple routine.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 src/mesa/drivers/dri/i965/brw_draw.c         |  6 +-----
 src/mesa/drivers/dri/i965/brw_state_upload.c | 11 +++++------
 src/mesa/drivers/dri/i965/gen7_sol_state.c   |  6 +-----
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  9 ++++-----
 4 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index c3f92c74cb..c497e4b3e8 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -247,11 +247,7 @@ brw_emit_prim(struct brw_context *brw,
          brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
                                I915_GEM_DOMAIN_VERTEX, 0,
                                prim->indirect_offset + 12);
-         BEGIN_BATCH(3);
-         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-         OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
-         OUT_BATCH(0);
-         ADVANCE_BATCH();
+         brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
       }
    } else {
       indirect_flag = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 629fb12a49..1f45da07bc 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -40,6 +40,7 @@
 #include "brw_gs.h"
 #include "brw_wm.h"
 #include "brw_cs.h"
+#include "brw_pipelined_register.h"
 #include "main/framebuffer.h"
 
 static const struct brw_tracked_state *gen4_atoms[] =
@@ -399,12 +400,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
    /* Recommended optimization for Victim Cache eviction in pixel backend. */
    if (brw->gen >= 9) {
-      BEGIN_BATCH(3);
-      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-      OUT_BATCH(GEN7_CACHE_MODE_1);
-      OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
-                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
-      ADVANCE_BATCH();
+      brw_load_register_imm32(brw,
+                              GEN7_CACHE_MODE_1,
+                              REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+                              GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
    }
 
    if (brw->gen >= 8) {
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index d6c4d1a5c8..1970732be0 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -512,11 +512,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
    /* Reset the SOL buffer offset registers. */
    if (brw->gen == 7 && brw->has_pipelined_so) {
       for (int i = 0; i < 4; i++) {
-         BEGIN_BATCH(3);
-         OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-         OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
-         OUT_BATCH(0);
-         ADVANCE_BATCH();
+         brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
       }
    }
 
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index ea79ab7346..892c97fd85 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -25,6 +25,7 @@
 #include "intel_fbo.h"
 #include "intel_resolve_map.h"
 #include "brw_context.h"
+#include "brw_pipelined_register.h"
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_wm.h"
@@ -346,11 +347,9 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
                                render_cache_flush);
 
    /* CACHE_MODE_1 is a non-privileged register. */
-   BEGIN_BATCH(3);
-   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
-   OUT_BATCH(GEN7_CACHE_MODE_1);
-   OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
-   ADVANCE_BATCH();
+   brw_load_register_imm32(brw,
+                           GEN7_CACHE_MODE_1,
+                           GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
 
    /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
     * Flush bits is often necessary.  We do it regardless because it's easier.
-- 
2.11.0