[Mesa-dev] [PATCH 04/11] radeonsi: add SI_CPDMA_SKIP_BO_LIST_UPDATE

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

the next commit will use it in a clever way, because the CP DMA prefetch
doesn't need this.
---
 src/gallium/drivers/radeonsi/si_cp_dma.c | 24 ++++++++++++++----------
 src/gallium/drivers/radeonsi/si_pipe.h   |  1 +
 2 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index f06b8dd..4c79dfe 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -126,36 +126,40 @@ static unsigned get_tc_l2_flag(struct si_context *sctx, enum r600_coherency cohe
 {
 	return coher == R600_COHERENCY_SHADER &&
 	       sctx->b.chip_class >= CIK ? CP_DMA_USE_L2 : 0;
 }
 
 static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst,
 			      struct pipe_resource *src, unsigned byte_count,
 			      uint64_t remaining_size, unsigned user_flags,
 			      bool *is_first, unsigned *packet_flags)
 {
-	/* Count memory usage in so that need_cs_space can take it into account. */
-	r600_context_add_resource_size(&sctx->b.b, dst);
-	if (src)
-		r600_context_add_resource_size(&sctx->b.b, src);
+	if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
+		/* Count memory usage in so that need_cs_space can take it into account. */
+		r600_context_add_resource_size(&sctx->b.b, dst);
+		if (src)
+			r600_context_add_resource_size(&sctx->b.b, src);
+	}
 
 	if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
 		si_need_cs_space(sctx);
 
 	/* This must be done after need_cs_space. */
-	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
-				  (struct r600_resource*)dst,
-				  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
-	if (src)
+	if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
-					  (struct r600_resource*)src,
-					  RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
+					  (struct r600_resource*)dst,
+					  RADEON_USAGE_WRITE, RADEON_PRIO_CP_DMA);
+		if (src)
+			radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+						  (struct r600_resource*)src,
+						  RADEON_USAGE_READ, RADEON_PRIO_CP_DMA);
+	}
 
 	/* Flush the caches for the first copy only.
 	 * Also wait for the previous CP DMA operations.
 	 */
 	if (!(user_flags & SI_CPDMA_SKIP_GFX_SYNC) && sctx->b.flags)
 		si_emit_cache_flush(sctx);
 
 	if (!(user_flags & SI_CPDMA_SKIP_SYNC_BEFORE) && *is_first)
 		*packet_flags |= CP_DMA_RAW_WAIT;
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index cecbc3b..64218ee 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -365,20 +365,21 @@ void si_resource_copy_region(struct pipe_context *ctx,
 			     unsigned dstx, unsigned dsty, unsigned dstz,
 			     struct pipe_resource *src,
 			     unsigned src_level,
 			     const struct pipe_box *src_box);
 
 /* si_cp_dma.c */
 #define SI_CPDMA_SKIP_CHECK_CS_SPACE	(1 << 0) /* don't call need_cs_space */
 #define SI_CPDMA_SKIP_SYNC_AFTER	(1 << 1) /* don't wait for DMA after the copy */
 #define SI_CPDMA_SKIP_SYNC_BEFORE	(1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
 #define SI_CPDMA_SKIP_GFX_SYNC		(1 << 3) /* don't flush caches and don't wait for PS/CS */
+#define SI_CPDMA_SKIP_BO_LIST_UPDATE	(1 << 4) /* don't update the BO list */
 
 void si_copy_buffer(struct si_context *sctx,
 		    struct pipe_resource *dst, struct pipe_resource *src,
 		    uint64_t dst_offset, uint64_t src_offset, unsigned size,
 		    unsigned user_flags);
 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
 			      uint64_t offset, unsigned size);
 void si_init_cp_dma_functions(struct si_context *sctx);
 
 /* si_debug.c */
-- 
2.7.4