[Mesa-dev] [PATCH 01/11] gallium/radeon: adjust constraints for linear texture layout selection

[Marek Olšák]

On Jan 18, 2017 3:42 AM, "Michel Dänzer" <michel at daenzer.net> wrote:

On 18/01/17 07:47 AM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> ---
>  src/gallium/drivers/radeon/r600_texture.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
> index cba4e7d..971e40a 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1177,21 +1177,24 @@ r600_choose_tiling(struct r600_common_screen
*rscreen,
>               if (rscreen->chip_class >= SI &&
>                   (templ->bind & PIPE_BIND_CURSOR))
>                       return RADEON_SURF_MODE_LINEAR_ALIGNED;
>
>               if (templ->bind & PIPE_BIND_LINEAR)
>                       return RADEON_SURF_MODE_LINEAR_ALIGNED;
>
>               /* Textures with a very small height are recommended to be
linear. */
>               if (templ->target == PIPE_TEXTURE_1D ||
>                   templ->target == PIPE_TEXTURE_1D_ARRAY ||
> -                 templ->height0 <= 4)
> +                 templ->height0 == 1 ||
> +                 /* Assume that the linear alignment has to be 64
texels. */
> +                 (templ->width0 > 32 &&
> +                  templ->height0 <= 4))
>                       return RADEON_SURF_MODE_LINEAR_ALIGNED;

This needs more explanation in the code comment and/or commit log as to
the motivation for / purpose of the change.


Let's drop this patch. It's not correct. A linear pitch is aligned to 64
bytes, not elements. The idea was that a 4x4 32bpp texture could fit in a
cache line if it's 1D tiled, and 4 cache lines if if it's linear.

Marek



--
Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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