[Mesa-dev] [PATCH 10/27] i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust

[Jason Ekstrand]

On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <
topi.pohjolainen at gmail.com> wrote:

> Hardware state setup only needs offset and pitch and ignores the
> rest.
>

True... But it seems a a bit sketchy to lie to blorp even if the lie is
ok.  This isn't a NAK, just a comment for now.  I need to read further to
get more context.


> Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c | 57 ++++++++++++------------------
> -----
>  1 file changed, 20 insertions(+), 37 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index ecf27a1..2001cf3 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -107,36 +107,6 @@ brw_blorp_init(struct brw_context *brw)
>  }
>
>  static void
> -apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
> -                              struct intel_mipmap_tree *mt,
> -                              uint32_t lod,
> -                              uint32_t *offset)
> -{
> -   assert(mt->array_layout == ALL_SLICES_AT_EACH_LOD);
> -
> -   if (mt->format == MESA_FORMAT_S_UINT8) {
> -      /* Note: we can't compute the stencil offset using
> -       * intel_miptree_get_aligned_offset(), because the miptree
> -       * claims that the region is untiled even though it's W tiled.
> -       */
> -      *offset = mt->level[lod].level_y * mt->pitch +
> -                mt->level[lod].level_x * 64;
> -   } else {
> -      *offset = intel_miptree_get_aligned_offset(mt,
> -                                                 mt->level[lod].level_x,
> -                                                 mt->level[lod].level_y);
> -   }
> -
> -   surf->logical_level0_px.width = minify(surf->logical_level0_px.width,
> lod);
> -   surf->logical_level0_px.height = minify(surf->logical_level0_px.height,
> lod);
> -   surf->phys_level0_sa.width = minify(surf->phys_level0_sa.width, lod);
> -   surf->phys_level0_sa.height = minify(surf->phys_level0_sa.height,
> lod);
> -   surf->levels = 1;
> -   surf->array_pitch_el_rows =
> -      ALIGN(surf->phys_level0_sa.height, surf->image_alignment_el.
> height);
> -}
> -
> -static void
>  blorp_surf_for_miptree(struct brw_context *brw,
>                         struct blorp_surf *surf,
>                         struct intel_mipmap_tree *mt,
> @@ -181,10 +151,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
>         * hacks inside the i965 driver.
>         *
>         * See also gen6_depth_stencil_state.c
> +       *
> +       * Note: we can't compute the stencil offset using
> +       * intel_miptree_get_aligned_offset(), because the miptree
> +       * claims that the region is untiled even though it's W tiled.
> +       *
> +       * In stencil state setup only surf->row_pitch and surf->addr get
> +       * consulted. Otherwise surf is ignored and there is no need to
> adjust
> +       * it any further.  See blorp_emit_depth_stencil_config().
>         */
> -      uint32_t offset;
> -      apply_gen6_stencil_hiz_offset(&tmp_surfs[0], mt, *level, &offset);
> -      surf->addr.offset += offset;
> +      surf->addr.offset += (mt->level[*level].level_y * mt->pitch +
> +                            mt->level[*level].level_x * 64);
>        *level = 0;
>     }
>
> @@ -254,11 +231,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
>                     hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD);
>
>              /* gen6 requires the HiZ buffer to be manually offset to the
> -             * right location.  We could fixup the surf but it doesn't
> -             * matter since most of those fields don't matter.
> +             * right location.
> +             * In depth state setup only surf->aux_surf.row_pitch gets
> +             * consulted. Otherwise surf->aux_surf is ignored and there is
> +             * no need to adjust it.  See blorp_emit_depth_stencil_
> config().
> +             *
> +             * surf->aux_surf.row_pitch in turn is set by
> +             * intel_miptree_get_aux_isl_surf().
>               */
> -            apply_gen6_stencil_hiz_offset(aux_surf, hiz_mt, *level,
> -                                          &surf->aux_addr.offset);
> +            surf->aux_addr.offset = intel_miptree_get_aligned_
> offset(hiz_mt,
> +                                       hiz_mt->level[*level].level_x,
> +                                       hiz_mt->level[*level].level_y);
>              assert(hiz_mt->pitch == aux_surf->row_pitch);
>           }
>        }
> --
> 2.5.5
>
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