[Mesa-dev] [PATCH 04/17] radeonsi: update dirty_level_mask only after the first draw after FB change
Marek Olšák
maraeo at gmail.com
Thu Jan 26 16:04:20 UTC 2017
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 2 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 52 +++++++++++++++-------------
3 files changed, 31 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 421e2a4..6558474 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -170,20 +170,21 @@ struct si_framebuffer {
unsigned compressed_cb_mask;
unsigned colorbuf_enabled_4bit;
unsigned spi_shader_col_format;
unsigned spi_shader_col_format_alpha;
unsigned spi_shader_col_format_blend;
unsigned spi_shader_col_format_blend_alpha;
unsigned color_is_int8; /* bitmask */
unsigned dirty_cbufs;
bool dirty_zsbuf;
bool any_dst_linear;
+ bool do_update_surf_dirtiness;
};
struct si_clip_state {
struct r600_atom atom;
struct pipe_clip_state state;
};
struct si_sample_locs {
struct r600_atom atom;
unsigned nr_samples;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 01edff9..df4b813 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2480,20 +2480,21 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
assert(0);
}
constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
}
sctx->need_check_render_feedback = true;
sctx->do_update_shaders = true;
+ sctx->framebuffer.do_update_surf_dirtiness = true;
}
static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
unsigned cb_color_info = 0;
@@ -3526,20 +3527,21 @@ static void si_set_tess_state(struct pipe_context *ctx,
pipe_resource_reference(&cb.buffer, NULL);
}
static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
{
struct si_context *sctx = (struct si_context *)ctx;
sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_FLUSH_AND_INV_CB;
+ sctx->framebuffer.do_update_surf_dirtiness = true;
}
/* This only ensures coherency for shader image/buffer stores. */
static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
{
struct si_context *sctx = (struct si_context *)ctx;
/* Subsequent commands must wait for all shader invocations to
* complete. */
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index d296874..db671c9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -985,20 +985,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
return;
}
/* Re-emit the framebuffer state if needed. */
dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
sctx->b.last_dirty_fb_counter = dirty_fb_counter;
sctx->framebuffer.dirty_cbufs |=
((1 << sctx->framebuffer.state.nr_cbufs) - 1);
sctx->framebuffer.dirty_zsbuf = true;
+ sctx->framebuffer.do_update_surf_dirtiness = true;
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
}
/* Invalidate & recompute texture descriptors if needed. */
dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
si_update_all_texture_descriptors(sctx);
}
@@ -1181,46 +1182,49 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Workaround for a VGT hang when streamout is enabled.
* It must be done after drawing. */
if ((sctx->b.family == CHIP_HAWAII ||
sctx->b.family == CHIP_TONGA ||
sctx->b.family == CHIP_FIJI) &&
r600_get_strmout_en(&sctx->b)) {
sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
}
- /* Set the depth buffer as dirty. */
- if (sctx->framebuffer.state.zsbuf) {
- struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
- struct r600_texture *rtex = (struct r600_texture *)surf->texture;
+ if (sctx->framebuffer.do_update_surf_dirtiness) {
+ /* Set the depth buffer as dirty. */
+ if (sctx->framebuffer.state.zsbuf) {
+ struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
+ struct r600_texture *rtex = (struct r600_texture *)surf->texture;
- if (!rtex->tc_compatible_htile)
- rtex->dirty_level_mask |= 1 << surf->u.tex.level;
-
- if (rtex->surface.flags & RADEON_SURF_SBUFFER)
- rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
- }
- if (sctx->framebuffer.compressed_cb_mask) {
- struct pipe_surface *surf;
- struct r600_texture *rtex;
- unsigned mask = sctx->framebuffer.compressed_cb_mask;
-
- do {
- unsigned i = u_bit_scan(&mask);
- surf = sctx->framebuffer.state.cbufs[i];
- rtex = (struct r600_texture*)surf->texture;
-
- if (rtex->fmask.size)
+ if (!rtex->tc_compatible_htile)
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
- if (rtex->dcc_gather_statistics)
- rtex->separate_dcc_dirty = true;
- } while (mask);
+
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+ rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
+ }
+ if (sctx->framebuffer.compressed_cb_mask) {
+ struct pipe_surface *surf;
+ struct r600_texture *rtex;
+ unsigned mask = sctx->framebuffer.compressed_cb_mask;
+
+ do {
+ unsigned i = u_bit_scan(&mask);
+ surf = sctx->framebuffer.state.cbufs[i];
+ rtex = (struct r600_texture*)surf->texture;
+
+ if (rtex->fmask.size)
+ rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+ if (rtex->dcc_gather_statistics)
+ rtex->separate_dcc_dirty = true;
+ } while (mask);
+ }
+ sctx->framebuffer.do_update_surf_dirtiness = false;
}
pipe_resource_reference(&ib.buffer, NULL);
sctx->b.num_draw_calls++;
if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
sctx->b.num_spill_draw_calls++;
}
void si_trace_emit(struct si_context *sctx)
{
--
2.7.4
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