[Mesa-dev] [PATCH 05/17] radeonsi: also prefetch compute shaders

[Marek Olšák]

From: Marek Olšák <marek.olsak at amd.com>

---
 src/gallium/drivers/radeonsi/si_compute.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index fe29fb1..d05c488 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -365,20 +365,32 @@ static bool si_switch_compute_shader(struct si_context *sctx,
 		            "Total Scratch: %u bytes\n", sctx->scratch_waves,
 			    config->scratch_bytes_per_wave,
 			    config->scratch_bytes_per_wave *
 			    sctx->scratch_waves);
 
 		radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
 			      shader->scratch_bo, RADEON_USAGE_READWRITE,
 			      RADEON_PRIO_SCRATCH_BUFFER);
 	}
 
+	/* Prefetch the compute shader to TC L2.
+	 *
+	 * We should also prefetch graphics shaders if a compute dispatch was
+	 * the last command, and the compute shader if a draw call was the last
+	 * command. However, that would add more complexity and we're likely
+	 * to get a shader state change in that case anyway.
+	 */
+	if (sctx->b.chip_class >= CIK) {
+		cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
+					 0, program->shader.bo->b.b.width0);
+	}
+
 	shader_va = shader->bo->gpu_address + offset;
 	if (program->use_code_object_v2) {
 		/* Shader code is placed after the amd_kernel_code_t
 		 * struct. */
 		shader_va += sizeof(amd_kernel_code_t);
 	}
 
 	radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
 	                          RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
 
-- 
2.7.4