[Mesa-dev] [PATCH 66/92] ac/nir: move setting shader_info->fs.writes_memory to radv-specific code

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/amd/common/ac_nir_to_llvm.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 26490b3..9d06a19 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3329,23 +3329,20 @@ static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
 static void visit_image_store(struct ac_nir_context *ctx,
 			      nir_intrinsic_instr *instr)
 {
 	LLVMValueRef params[8];
 	char intrinsic_name[64];
 	const nir_variable *var = instr->variables[0]->var;
 	const struct glsl_type *type = glsl_without_array(var->type);
 	LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
 	LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
 
-	if (ctx->stage == MESA_SHADER_FRAGMENT)
-		ctx->nctx->shader_info->fs.writes_memory = true;
-
 	if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
 		params[0] = to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
 		params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, true, true);
 		params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
 						    ctx->ac.i32_0, ""); /* vindex */
 		params[3] = ctx->ac.i32_0; /* voffset */
 		params[4] = i1false;  /* glc */
 		params[5] = i1false;  /* slc */
 		ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
 				   params, 6, 0);
@@ -3393,23 +3390,20 @@ static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
 	const nir_variable *var = instr->variables[0]->var;
 
 	const char *base_name = "llvm.amdgcn.image.atomic";
 	const char *atomic_name;
 	LLVMValueRef coords;
 	char intrinsic_name[32], coords_type[8];
 	const struct glsl_type *type = glsl_without_array(var->type);
 	LLVMValueRef i1false = LLVMConstInt(ctx->ac.i1, 0, false);
 	LLVMValueRef i1true = LLVMConstInt(ctx->ac.i1, 1, false);
 
-	if (ctx->stage == MESA_SHADER_FRAGMENT)
-		ctx->nctx->shader_info->fs.writes_memory = true;
-
 	params[param_count++] = get_src(ctx, instr->src[2]);
 	if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
 		params[param_count++] = get_src(ctx, instr->src[3]);
 
 	if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
 		params[param_count++] = get_sampler_desc(ctx, instr->variables[0],
 							 AC_DESC_BUFFER, true, true);
 		coords = params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
 									ctx->ac.i32_0, ""); /* vindex */
 		params[param_count++] = ctx->ac.i32_0; /* voffset */
@@ -4059,20 +4053,23 @@ static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
 	struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
 	struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
 	unsigned offset = binding->offset;
 	unsigned stride = binding->size;
 	unsigned type_size;
 	LLVMBuilderRef builder = ctx->builder;
 	LLVMTypeRef type;
 
 	assert(base_index < layout->binding_count);
 
+	if (write && ctx->stage == MESA_SHADER_FRAGMENT)
+		ctx->shader_info->fs.writes_memory = true;
+
 	switch (desc_type) {
 	case AC_DESC_IMAGE:
 		type = ctx->v8i32;
 		type_size = 32;
 		break;
 	case AC_DESC_FMASK:
 		type = ctx->v8i32;
 		offset += 32;
 		type_size = 32;
 		break;
-- 
2.9.3