[Mesa-dev] [PATCH 3/3] i965: Disable stencil cache optimization combining two 4x2 blocks

[Topi Pohjolainen]

>From the BDW PRM, Volume 15, Workarounds:

KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.

W/A: Disable 4x4 RCPFE STC optimization and therefore only send one
     valid 4x4 to STC on 4x4 interface. This will require setting bit
     6 of reg. 0x7004. Must be done at boot and all save/restore paths.

>From the SKL PRM, Volume 16, Workarounds:

0556 KMD Wa4x4STCOptimizationDisable HIZ/STC hang in hawx frames.

W/A: Disable 4 x4 RCPFE STC optimization and therefore only send
     one valid 4x4 to STC on 4x4 interface.  This will require setting
     bit 6 of reg. 0x7004. Must be done at boot and all save/restore
     paths.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h      | 5 ++++-
 src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4abb790612..248512e01a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1611,11 +1611,14 @@ enum brw_pixel_shader_coverage_mask_mode {
 
 #define GEN7_CACHE_MODE_1               0x7004
 # define GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
+# define GEN8_4X4_RCPFE_STC_OPTIMIZATION_DISABLE (1 << 6)
 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
 # define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
 # define GEN8_HIZ_PMA_MASK_BITS \
-   REG_MASK(GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
+   REG_MASK(GEN8_4X4_RCPFE_STC_OPTIMIZATION_DISABLE | \
+            GEN8_HIZ_NP_PMA_FIX_ENABLE | \
+            GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE)
 
 #define GEN7_GT_MODE                    0x7008
 # define GEN9_SUBSLICE_HASHING_8x8      (0 << 8)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7b31aad170..4149a3d5d4 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -71,6 +71,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       OUT_BATCH(GEN7_CACHE_MODE_1);
       OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
                 REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
+                REG_MASK(GEN8_4X4_RCPFE_STC_OPTIMIZATION_DISABLE) |
                 GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
                 GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
       ADVANCE_BATCH();
-- 
2.11.0