[Mesa-dev] [PATCH 1/2] amd/common: move ac_build_phi from radeonsi

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

---
 src/amd/common/ac_llvm_build.c           | 14 ++++++++++++++
 src/amd/common/ac_llvm_build.h           |  5 +++++
 src/gallium/drivers/radeonsi/si_shader.c | 20 +++-----------------
 3 files changed, 22 insertions(+), 17 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 71468df2dbc..51fb009be8b 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -245,20 +245,34 @@ void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned bufsize)
 		break;
 	case LLVMFloatTypeKind:
 		snprintf(buf, bufsize, "f32");
 		break;
 	case LLVMDoubleTypeKind:
 		snprintf(buf, bufsize, "f64");
 		break;
 	}
 }
 
+/**
+ * Helper function that builds an LLVM IR PHI node and immediately adds
+ * incoming edges.
+ */
+LLVMValueRef
+ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
+	     unsigned count_incoming, LLVMValueRef *values,
+	     LLVMBasicBlockRef *blocks)
+{
+	LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
+	LLVMAddIncoming(phi, values, blocks, count_incoming);
+	return phi;
+}
+
 /* Prevent optimizations (at least of memory accesses) across the current
  * point in the program by emitting empty inline assembly that is marked as
  * having side effects.
  *
  * Optionally, a value can be passed through the inline assembly to prevent
  * LLVM from hoisting calls to ReadNone functions.
  */
 void
 ac_build_optimization_barrier(struct ac_llvm_context *ctx,
 			      LLVMValueRef *pvgpr)
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 3f93551330c..1d6dc0ab2f5 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -78,20 +78,25 @@ LLVMValueRef ac_to_integer(struct ac_llvm_context *ctx, LLVMValueRef v);
 LLVMTypeRef ac_to_float_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
 LLVMValueRef ac_to_float(struct ac_llvm_context *ctx, LLVMValueRef v);
 
 LLVMValueRef
 ac_build_intrinsic(struct ac_llvm_context *ctx, const char *name,
 		   LLVMTypeRef return_type, LLVMValueRef *params,
 		   unsigned param_count, unsigned attrib_mask);
 
 void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned bufsize);
 
+LLVMValueRef
+ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
+	     unsigned count_incoming, LLVMValueRef *values,
+	     LLVMBasicBlockRef *blocks);
+
 void ac_build_optimization_barrier(struct ac_llvm_context *ctx,
 				   LLVMValueRef *pvgpr);
 
 LLVMValueRef ac_build_ballot(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_all(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_any(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index d012c19a58a..c11a4ebeade 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -227,34 +227,20 @@ unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
 		assert(index < 8);
 		assert(SI_MAX_IO_GENERIC + 10 + index < 64);
 		return SI_MAX_IO_GENERIC + 10 + index;
 	default:
 		assert(!"invalid semantic name");
 		return 0;
 	}
 }
 
 /**
- * Helper function that builds an LLVM IR PHI node and immediately adds
- * incoming edges.
- */
-static LLVMValueRef
-build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
-	  unsigned count_incoming, LLVMValueRef *values,
-	  LLVMBasicBlockRef *blocks)
-{
-	LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
-	LLVMAddIncoming(phi, values, blocks, count_incoming);
-	return phi;
-}
-
-/**
  * Get the value of a shader input parameter and extract a bitfield.
  */
 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
 				 unsigned param, unsigned rshift,
 				 unsigned bitwidth)
 {
 	struct gallivm_state *gallivm = &ctx->gallivm;
 	LLVMValueRef value = LLVMGetParam(ctx->main_fn,
 					  param);
 
@@ -2915,29 +2901,29 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
 		LLVMBasicBlockRef blocks[2] = {
 			LLVMGetInsertBlock(builder),
 			ctx->merged_wrap_if_state.entry_block
 		};
 		LLVMValueRef values[2];
 
 		lp_build_endif(&ctx->merged_wrap_if_state);
 
 		values[0] = rel_patch_id;
 		values[1] = LLVMGetUndef(ctx->i32);
-		rel_patch_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
+		rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
 
 		values[0] = tf_lds_offset;
 		values[1] = LLVMGetUndef(ctx->i32);
-		tf_lds_offset = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
+		tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
 
 		values[0] = invocation_id;
 		values[1] = ctx->i32_1; /* cause the epilog to skip threads */
-		invocation_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
+		invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
 	}
 
 	/* Return epilog parameters from this function. */
 	LLVMValueRef ret = ctx->return_value;
 	unsigned vgpr;
 
 	if (ctx->screen->b.chip_class >= GFX9) {
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
 					  8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
 		ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_addr_base64k,
-- 
2.11.0