[Mesa-dev] [PATCH 00/13] nir/vtn/compiler: first batch of compute support

Rob Clark robdclark at gmail.com
Wed Feb 28 19:51:30 UTC 2018

This is by no means everything needed for clover/OpenCL.. but I took
a bit of time this morning to extract some parts of our growing stack
of patches which where plausibly mergable (or at least not complete
hacks), with the idea that review could start in parallel with further
clover/compute hacking.

In particular, it could be useful to at least (once reviewed) merge the
new nir intrinsics, since those would unblock landing the corresponding
nvir and ir3 patches which implement the new intrinsics.

The new intrinsics are:
 - load_param - for compute kernels the entrypoint can have parameters
   and we need a way to load them
 - load/store_global - for dereferencing pointers

In the case of pointers, I punted on dealing with local vs global
pointers.  AFAIU with amd/nv GPUs local memory can be mapped into a
single address space alongside global pointers, so they might not really
have to care about pointers into local memory.  For ir3, there *are*
different instructions for local vs global.  One option could be to
emulate a flat address space using the high bits of a pointer (at least
that would work in 64b mode, not sure about 32b mode).  Other option is
"fat" pointers (ie. storing a pointer in a vec2 or two registers, where
one value indicates the pointer type), which at least works ok as long
as everything is in SSA.  But not sure how that would work if you had
to store a pointer value to memory.  But bigger fires, so I punted on
that for now.

The last patch, which adds load/store_global support to vtn, is just RFC.
Mostly looking for suggestions on how best to handle "logical" pointers
(ie. gfx/vk shaders) vs "physical" pointers (ie. compute/kernel).

Karol Herbst (5):
  nir: allow 64 bit shifts
  nir: add load_param
  nir: add load/store_global intrinsics
  nir/vtn: implement BuiltInGlobalSize
  compiler: int8/uint8 support

Rob Clark (8):
  nir: kernel entrypoints can have arguments
  nir: expose 'C' wrappers for std430 size/alignment
  nir/vtn: implement SpvOpCopyMemorySized
  nir/vtn: handle WorkGroupSize for kernels
  nir/vtn: add OpLifetime*
  nir/vtn: add OpConvertPtrToU
  nir/vtn: print extension name in fail msg
  RFC: nir/vtn: "raw" pointer support

 src/compiler/builtin_type_macros.h              |  10 +
 src/compiler/glsl/ast_to_hir.cpp                |   2 +
 src/compiler/glsl/ir_clone.cpp                  |   2 +
 src/compiler/glsl/link_uniform_initializers.cpp |   2 +
 src/compiler/glsl_types.cpp                     |  33 ++++
 src/compiler/glsl_types.h                       |   4 +
 src/compiler/nir/nir.h                          |   5 +-
 src/compiler/nir/nir_intrinsics.h               |  10 +-
 src/compiler/nir/nir_lower_io.c                 |  13 +-
 src/compiler/nir/nir_lower_system_values.c      |   8 +
 src/compiler/nir/nir_opcodes.py                 |   6 +-
 src/compiler/nir/nir_search.c                   |   2 +
 src/compiler/nir_types.cpp                      |  24 +++
 src/compiler/nir_types.h                        |  10 +
 src/compiler/shader_enums.c                     |   1 +
 src/compiler/shader_enums.h                     |   2 +
 src/compiler/spirv/spirv_to_nir.c               |  83 +++++++-
 src/compiler/spirv/vtn_alu.c                    |   1 +
 src/compiler/spirv/vtn_private.h                |  21 +-
 src/compiler/spirv/vtn_variables.c              | 247 +++++++++++++++++++++---
 src/intel/compiler/brw_fs.cpp                   |   3 +
 src/intel/compiler/brw_shader.cpp               |   4 +
 src/intel/compiler/brw_vec4_visitor.cpp         |   2 +
 src/mesa/program/ir_to_mesa.cpp                 |   4 +
 src/mesa/state_tracker/st_glsl_types.cpp        |   2 +
 25 files changed, 459 insertions(+), 42 deletions(-)


More information about the mesa-dev mailing list